1 Bringing it all together: Exploring the EVB Today: First Hour: Bringing it all together by exploring the EVB –Section of Huang’s Textbook –In-class Activity #1 Second Hour: Answers to your questions

2 Internal Bus #1 M A R Memory Address Bus M B R Internal Bus #2 Data Bus Register File (A, B, IX, IY, IR) MUX CCRCCR P C Recap: M6811 Datapath ALU A 16 - A 0 D 7 - D 0 The datapath unit consists of registers, buses connecting them, and the ALU

3 Internal Bus #1 M A R Memory Address Bus M B R Internal Bus #2 Data Bus Register File (A, B, IX, IY, IR) MUX CCRCCR P C Recap: M6811 Control Unit ALU A 16 - A 0 D 7 - D 0 Control Unit

4 E R/W AS AD7 - AD0 68HC11 PC7- PC0 A15 - A8 PB7- PB0 MODB MODA Bus Recap: Time-Multiplexed Bus 1 1 Other pins not shown

5 E R/W A15-A8 AD7-AD0LO-ADDRDATA AS XTAL Recap: Bus Timing Diagram HI ADDR Magic Moment #1 Magic Moment #2

6 Recap: De-multiplexing the Address E R/W AS AD7-AD0 68HC11 PC7-PC0 A15-A8 PB7-PB0 MODB MODA Bus 1 1 Other pins not shown D0-D7 Q0-Q7 A0-A7 LS 373 LE Address A0-A7 latched on the falling edge of AS OE 0 Magic Moment #1

7 Bus Interfacing Summary Step 1: Bus Demultiplexing –Use address strobe (AS) and a latch to Demultiplex the address and data lines Step 2: Address Decoding –Use Boolean logic to decode the desired address Chip Select = Compare(A 15 … A 0 = desired address ) AND (E = 1) Step 3: Generate Read/write control signal – Use the second half of E cycle to generate Read/Write signal for RAM chip

8 Recap: Memory Interfacing A2 A1 A0 E3 E2E1 A15 A14 A13 E R/W A12 – A8 AS AD7-AD0 LE D7-D0 O7-O0 OE I/O8 - I/O1 WE CS1 CS2 V DD O2 A12-A0 OE 8K RAM Decoder 68HC11 Latch 74LS00 74LS04 $ $5FFF

9 Recap: Memory-mapped I/O Every I/O device “appears” to the CPU as a memory location –Use LDAA and STAA for input/output Several useful I/O devices, and some memory devices are already interfaced for us on the 6811 chip.

10 Event counter Generate periodic interrupts Periodically check the chip Put code in ROM Put non- volatile data in EEPROM SPI for inter- connecting 6811’s SCI for connecting to host computer Input analog signals Fancy general- purpose timer Bus for expansion

11 Port Replacement Unit (PRU) Recovers PORTB and PORTC in expanded mode E R/W AS AD7-AD0 68HC11 PC7-PC0 A15-A8 PB7-PB0 MODB MODA 1 1 Other pins not shown PORTB PORTC Port Replacement Unit (PRU) STRA STRB

12 Building The EVB 6811 Latch PRU 8K ROM 8K RAM Port A PD0 - 5 Port E Port B Port C AD0 - AD7 A0 - A7 A8 – A15 A0 – A15 AD0 - AD7

13 Adding Communication ACIA 6811 Latch PRU 8K ROM 8K RAM Terminal (P2) Host Computer (P3) RS-232 Drivers & Receivers Port A PD0 - 5 Port E Port B Port C AD0 - AD7 A0 - A7 A8 – A15 A0 – A15 AD0 - AD7 PD1 PD0 TX RX Control RX TX Control RX TX

14 Software Picture of EVB Memory Map –Specifies what addresses are for what BUFFALO Utility Routines –Useful for development & debugging BUFFALO command interpreter Interrupt vector jump table in RAM

15 Do Activity #1 Now Due: End of Class Today. RETAIN THE LAST PAGE(S) (#3 onwards)!! During studio time this week: Catch up with experiments. Summarize reading of Chapter 4, Chapter 5 (sections ), and Chapter 6 (6.1 – 6.7) That’s it. No more new material!