1 CS151: Digital Design Chapter 3: Combinational Logic Design 3-2 Beginning Hierarchical Design 3-3 Technology Mapping

CS Hierarchical Design To control the complexity of the function mapping inputs to outputs, divide and conquer:  Decompose the function into smaller pieces called blocks  Decompose each block’s function into smaller blocks, repeating as necessary until all blocks are small enough  Any block not decomposed is called a primitive block  The collection of all blocks including the decomposed ones is a hierarchy

CS Example 1: Hierarchy for 16-Word by 1 Bit RAM Chip 16-Word by 1 Bit RAM Chip 4-to-16 Decoder Static RAM Cell C S R Q Q C R Q Q C S R Q S Q SR-Flip-Flop S R Q Q C SR- Latch

CS Example 2: Hierarchy for Parity Tree X 0 X 1 X 2 X 3 X 4 X 5 X 6 X 7 X 8 Z O 9-Input odd function (a) Symbol for circuit B O 3-Input odd function A 0 A 1 A 2 B O 3-Input odd function A 0 A 1 A 2 B O 3-Input odd function A 0 A 1 A 2 B O 3-Input odd function A 0 A 1 A 2 X 0 X 1 X 2 X 3 X 4 X 5 X 6 X 7 X 8 Z O (b) Circuit as interconnected 3-input odd function blocks interconnected exclusive-OR blocks B O A 0 A 1 A 2 (c) 3-input odd function circuit as (d) Exclusive-OR block as interconnected NANDs

CS Hierarchy for Parity Tree Example Example: 9-input parity tree  Top Level: 9 inputs, one output  2nd Level: Four 3-bit odd parity trees in two levels  3rd Level: Two 2-bit exclusive-OR functions  Primitives: Four 2-input NAND gates  Design requires 4 X 2 X 4 = 32 2-input NAND gates

CS Reusable Functions and CAD functional blocks Whenever possible, we try to decompose a complex design into common, reusable functional blocks These blocks  Reduce the complexity to present the circuit diagram  are verified and well-documented  are placed in libraries for future use

CS Top-Down versus Bottom-Up A top-down design proceeds from an abstract, high-level specification to a more and more detailed design by decomposition and successive refinement A bottom-up design starts with detailed primitive blocks and combines them into larger and more complex functional blocks Designs usually proceed from both directions simultaneously  Top-down design answers: What are we building?  Bottom-up design answers: How do we build it? Top-down controls complexity while bottom-up focuses on the details

CS Technology Mapping Mapping Procedures  To NAND gates  To NOR gates  Mapping to multiple types of logic blocks in covered in the reading supplement: Advanced Technology Mapping.

CS NAND Gate The basic NAND gate has the following symbol, illustrated for three inputs:  AND-Invert (NAND) NAND represents NOT AND, i. e., the AND function with a NOT applied. The symbol shown is an AND- Invert. The small circle (“bubble”) represents the invert function. What does the truth table for NAND look like? X Y Z ZYX)Z,Y,X(F 

CS NAND Gates (continued) Applying DeMorgan's Law gives Invert-OR 1 (NAND) This NAND symbol is called Invert-OR, since inputs are inverted and then ORed together. AND-Invert 2 and Invert-OR both represent the NAND gate. Having both makes visualization of circuit function easier. A NAND gate with one input degenerates to an inverter. X Y Z ZYX)Z,Y,X(F  1.Also called NOT-OR 2.Also called AND-NOT

CS Mapping to NAND gates Assumptions:  Gate loading and delay are ignored  Cell library contains an inverter and n-input NAND gates, n = 2, 3, …  An AND, OR, inverter schematic for the circuit is available The mapping is accomplished by:  Replacing AND and OR symbols,  Pushing inverters through circuit fan-out points, and  Canceling inverter pairs

CS NAND Mapping Algorithm 1. Replace ANDs and ORs: 2. Repeat the following pair of actions until there is at most one inverter between : a. A circuit input or driving NAND gate output, and b. The attached NAND gate inputs.

CS NAND Mapping Example

CS NOR Gate The basic NOR gate has the following symbol, illustrated for three inputs:  OR-Invert (NOR) NOR represents NOT - OR, i. e., the OR function with a NOT applied. The symbol shown is an OR- Invert. The small circle (“bubble”) represents the invert function. What does the truth table for NOR look like? X Y Z ZYX)Z,Y,X(F  + 

CS NOR Gate (continued) Applying DeMorgan's Law gives Invert-AND (NOR) This NOR symbol is called Invert-AND, since inputs are inverted and then ANDed together. OR-Invert and Invert-AND both represent the NOR gate. Having both makes visualization of circuit function easier. A NOR gate with one input degenerates to an inverter. X Y Z

CS Mapping to NOR gates Assumptions:  Gate loading and delay are ignored  Cell library contains an inverter and n-input NOR gates, n = 2, 3, …  An AND, OR, inverter schematic for the circuit is available The mapping is accomplished by:  Replacing AND and OR symbols,  Pushing inverters through circuit fan-out points, and  Canceling inverter pairs

CS NOR Mapping Algorithm 1. Replace ANDs and ORs: 2. Repeat the following pair of actions until there is at most one inverter between : a. A circuit input or driving NAND gate output, and b. The attached NAND gate inputs.

CS NOR Mapping Example