Carry-Lookahead, Carry-Select, & Hybrid Adders ECE 645: Lecture 2

Required Reading Chapter 6, Carry-Lookahead Adders Sections Chapter 7, Variations in Fast Adders Section 7.3, Carry-Select Adders. Chapter 28, Reconfigurable Arithmetic Section 28.2, Adder Designs for FPGAs. Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design

Carry-Lookahead Adders

Basic Signals Generate signal: g i = x i y i Propagate signal: p i = x i  y i Anihilate (absorb) signal: a i = x i y i = x i + y i Transfer signal: t i = g i + p i = a i = x i + y i c out =1 given c in = 1 c i+1 = g i + c i p i = g i + c i t i Carry recurrence

Unrolling Carry Recurrence c i = g i-1 + c i-1 p i-1 = = g i-1 + (g i-2 + c i-2 p i-2 )p i-1 = g i-1 + g i-2 p i-1 + c i-2 p i-2 p i-1 = = g i-1 + g i-2 p i-1 + (g i-3 + c i-3 p i-3 )p i-2 p i-1 = = g i-1 + g i-2 p i-1 + g i-3 p i-2 p i-1 + c i-3 p i-3 p i-2 p i-1 = = ….. = = g i-1 + g i-2 p i-1 + g i-3 p i-2 p i-1 + g i-4 p i-3 p i-2 p i-1 + … g 0 p 1 p 2 …p i-2 p i-1 + c 0 p 0 p 1 p 2 …p i-2 p i-1 = = g i-1 +  g k  p j + c 0  p j k=0 i-2 j=k+1 i-1 j=0 i-1

4-bit Carry-Lookahead Adder (1) c 4 = g 3 + g 2 p 3 + g 1 p 2 p 3 + g 0 p 1 p 2 p 3 + c 0 p 0 p 1 p 2 p 3 c 3 = g 2 + g 1 p 2 + g 0 p 1 p 2 + c 0 p 0 p 1 p 2 c 2 = g 1 + g 0 p 1 + c 0 p 0 p 1 c 1 = g 0 + c 0 p 0 s 0 = x 0  y 0  c 0 = p 0  c 0 s 1 = p 1  c 1 s 2 = p 2  c 2 s 3 = p 3  c 3

4-bit Carry-Lookahead Adder (2) c 4 = g 3 + c 3 p 3 c 3 = g 2 + g 1 p 2 + g 0 p 1 p 2 + c 0 p 0 p 1 p 2 c 2 = g 1 + g 0 p 1 + c 0 p 0 p 1 c 1 = g 0 + c 0 p 0 s 0 = x 0  y 0  c 0 = p 0  c 0 s 1 = p 1  c 1 s 2 = p 2  c 2 s 3 = p 3  c 3 3 gates less

4-bit Carry Network with Full Lookahead

4-bit Lookahead Carry Generator c i+3 = g i+2 + g i+1 p i+2 + g i p i+1 p i+2 + c i p i p i+1 p i+2 c i+2 = g i+1 + g i p i+1 + c i p i p i+1 c i+1 = g i + c i p i g [i..i+3] = g i+3 + g i+2 p i+3 + g i+1 p i+2 p i+3 + g i p i+1 p i+2 p i+3 p [i..i+3] = p i p i+1 p i+2 p i+3 Equations

4-bit Lookahead Carry Generator Schematic

4-bit Lookahead Carry Generator Symbol

CLA GEN c1c1 c2c2 c3c3 g [0,3] p [0,3] g0p0g0p0 g1p1g1p1 g2p2g2p2 g3p3g3p3 c0c0 CLA GEN c5c5 c6c6 c7c7 g [4,7] p [4,7] g4p4g4p4 g5p5g5p5 g6p6g6p6 g7p7g7p7 c4c4 CLA GEN c9c9 c 10 c 11 g [8,11] p [8,11] g8p8g8p8 g9p9g9p9 g 10 p 10 g 11 p 11 c8c8 CLA GEN c 13 c 14 c 15 g [12,15] P [12,15] g 12 p 12 g 13 p 13 g 14 p 14 g 15 p 15 c bit 2-level Carry Lookahead Adder CLA GEN g [0,15] p [0,15]

Operation of the 16-bit 2-level Carry Lookahead Adder (1) Delay Signals computed g i, p i Formulas g i = x i y i p i = x i  y i 1 gate delay i=0..15 g [i..i+3], p [i..i+3] i=0, 4, 8, 12 2 gate delays g [i..i+3] = g i+3 + g i+2 p i+3 + g i+1 p i+2 p i+3 + g i p i+1 p i+2 p i+3 p [i..i+3] = p i p i+1 p i+2 p i+3

Operation of the 16-bit 2-level Carry Lookahead Adder (2) Delay Signals computed Formulas c 4, c 8, c 12 g [0..15], p [0..15] 2 gate delays c 12 = g [8..11] + g [4..7] p [8..11] + g [0..3] p [4..7] p [8..11] + c 0 p [0..3] p [4..7] p [8..11] c 8 = g [4..7] + g [0..3] p [4..7] + c 0 p [0..3] p [4..7] c 4 = g [0..3] + c 0 p [0..3] g [0..15] = g [12..15] + g [8..11] p [12..15] + g [4..7] p [8..11] p [12..15] + g [0..3] p [4..7] p [8..11] p [12..15] p [0..15] = p [0..3] p [4..7] p [8..11] p [12..15]

Operation of the 16-bit 2-level Carry Lookahead Adder (3) Delay Signals computed Formulas c i+1, c i+2, c i+3 2 gate delays i = 4, 8, 12 c i+3 = g i+2 + g i+1 p i+2 + g i p i+1 p i+2 + c i p i p i+1 p i+2 c i+2 = g i+1 + g i p i+1 + c i p i p i+1 c i+1 = g i + c i p i i.e., c 5, c 6, c 7, c 9, c 10, c 11, c 13, c 14, c 15

Operation of the 16-bit 2-level Carry Lookahead Adder (4) Delay Signals computed Formulas s i+1, s i+2, s i+3 1 gate delay i = 4, 8, 12 s i = p i  c i i.e., s 5, s 6, s 7, s 9, s 10, s 11, s 13, s 14, s 15 Total: 8 gate levels in the CLA adder vs. 32 gate levels in the ripple carry adder

64-bit 3-level Carry Lookahead Adder g [16,19] p [16,19] c 16 g [20,23] p [20,23] c 20 g [24,27] p [24,27] c 24 g [28,31] p [28,31] c 28 CLA GEN g [16,31] p [16,31] CLA GEN c0c0 c 31 c 30 c 29 c 27 c 26 c 25 c 23 c 22 c 21 c 19 c 18 c 17 g [0,15] p [0,15] g [32,47] p [32,47] g [48,63] p [48,63] c 32 c 48 g [0,63] p [0,63]

Operation of the 64-bit 3-level Carry Lookahead Adder Delay Signals computed g i, p i 1 gate delay i=0..63 g [i..i+3], p [i..i+3] i=0, 4, 8, 12, …, 56, 60 2 gate delays Level 1 g [i..i+15], p [i..i+15] i=0, 16, 32, gate delays 3 c 16, c 32, c 48, g [0..63], p [0..63] 2 gate delays 2 1 PRE POST c 20, c 24, c 28, c 36, c 40, c 44, c 52, c 56, c 60 2 gate delays c 21, c 22, c 23, c 25, c 26, c 27, …, c 61, c 62, c 63 2 gate delays s 21, s 22, s 23, s 25, s 26, s 27, …, s 61, s 62, s 63 1 gate delay

Delay of a k-bit Carry-Lookahead Adder T lookahead-adder = 4 log 4 k k T lookahead-adder T ripple-carry-adder

Carry-Select Adders

One-level k-bit Carry-Select Adder

Cost & Latency Units: cost and delay of a single 2-to-1 multiplexer

Two-level k-bit Carry Select Adder

Possible Design of a Carry-Select Adder on an FPGA / 2 2 bits bits4 bits6 bits1 bit / 3 / 4 / 6

Hybrid Adders

A Hybrid Ripple-Carry/Carry-Lookahead Adder

A Hybrid Carry-Lookahead/Carry-Select Adder