30 September 2005, Frascati Anatoli Kachtchouk) 1 From CARDIAC version 2 to CARDIAC version 3 N.Bondar, A.Kachtchouk, P.Neustroev (PNPI)

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30 September 2005, Frascati Anatoli Kachtchouk) 4 Cathode Ampl. Anode Ampl. (only!) The detector current returns along the foil of the outer panel (only!) All cathodes are segmented in DCRO Wire strip 2 Cathode pads Where the detector currents return path in M3R1 (DCRO)? FC (only for Idet.) GND Bus Bar (only for Idigital) i(t) f(10-300)MHz Outer panel

30 September 2005, Frascati Anatoli Kachtchouk) 5 AmplDigital Blocking Capacitors on boards Vdd Bus Bar GND Bus Bar To Voltage Regulator (VR) MP To next FEB FEB DigitalAmpl FEB From VR Idet From wire To both cathodes Where the digital currents return path? e.g. two Front-End Boards (FEB) are shown for illustration 2 phases has to be considered: 1) Digital currents return through the lowest impedance provided by local blocking capacitors located near chips on FEB; 2) Charge recovering process: same currents from VR through Vdd/GND Bus Bar FC 2 layers in DCRO (very pure) 6 layers in SCRO 10 layers in WPC

30 September 2005, Frascati Anatoli Kachtchouk) 6 Log scale Linear scale Threshold scan

30 September 2005, Frascati Anatoli Kachtchouk) 7 EM pickup ! Log scale Threshold scan

30 September 2005, Frascati Anatoli Kachtchouk) 8 WPC#104 CARDIAC_neg.

30 September 2005, Frascati Anatoli Kachtchouk) 9 PWR connector (+2.5V/GND) LVDS connector (no GND) pin1 +/- pin1 2x7=14pin pin V pin8-14 GND pin1 Input 1-8 (bottom) 1x17=17pin Input 16-9 (bottom) 1x17=17pin CTRL-in 2x5=10pin CTRL-out 2x5=10pin Top view x8=16pin (with locks) A.Kashchuk P.Ciambrone pads to FC between A and D GND from v.2 to v.3 4 pads to FC between A and D GND

30 September 2005, Frascati Anatoli Kachtchouk) 10 Ampl Discr. Dialog Vdd D_GND A_GND R 4.3 Ohm Inp Proposed Ground and Vdd network. Input_stage_ground of CARIOCA chip (which is the detector GND, also extended to the corners on board and to guard ground between input pins) must be separated from other grounds and connected together close to the LV connector (incoming/outgoing GND). Install resistor 4.3 Ohm separating detector and digital GND (see slide 11), then 4 corners can be connected to FC (preventing instability). Blocking capacitors on VDD must be connected to the corresponding ground (digital to digital etc.), eliminate mixture in connections. CARIOCA

30 September 2005, Frascati Anatoli Kachtchouk) 11 There is pick-up from I2C bus (any line) to CARIOCA inputs: must be improved by extra measures D_GND Ampl Discr. Dialog A_GND R 4.3 Ohm Iinp CARIOCA Cdet Cpar I2C line Cin I noise Iinp = Inoise - Idet Idet The larger C det – the smaller I inp Possible solution – Organize power plane 1 for Cardiac chip and plane 2 for Dialog chip - Split ground plane for 2 parts

30 September 2005, Frascati Anatoli Kachtchouk) 12 Change LV connector to the previous type 14-pin (8 pins for ground, 6 for VDD) or another one to be incompatible to I2C connectors. Suggestions: CARIOCA polarity (2 jumpers on board) and Address (4 jumpers on board) have to be standard 2-pin 2.54mm jumpers to be easy reinstalled by hands. LVDS connector must be specified and installed on boards as a connector with locks GRES remove (it is already blocked by 100nF through R=0) Ground (pin 8) in the I2C bus in both connectors must be disconnected from the ground on board, similar to LVDS.

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30 September 2005, Frascati Anatoli Kachtchouk) 26 CARDIACv2.3. must be redesigned There is pick-up from I2C bus (any line) to CARIOCA inputs: must be shielded by ground layer. Input_stage_ground of CARIOCA chip (which is the detector GND, also extended to the corners on board and to guard ground between input pins) must be separated from other grounds and connected together close to the LV connector (incoming/outgoing GND). Install resistor 4.3 Ohm separating detector and digital GND (see slide 11), then 4 corners can be connected to FC (preventing instability). Blocking capacitors on VDD must be connected to the corresponding ground (digital to digital etc.), eliminate mixture in connections. CARIOCA polarity (2 jumpers on board) and Address (4 jumpers on board) have to be standard 2-pin 2.54mm jumpers to be easy reinstalled by hands. Change LV connector to the previous type 14-pin (8 pins for ground, 6 for VDD) or another one to be incompatible to I2C connectors. LVDS connector must be specified and installed on boards as a connector with locks. Ground (pin 8) in the I2C bus in both connectors must be disconnected from the ground on board, similar to LVDS which have no ground. Note: the same on SB. GRES remove (it is already blocked by 100nF through R=0) Remove personal names from pcb (this is at least collective property, e.g. my as well) There are also many other remarks: e.g. increase gaps between Vdd and GND; diameter of holes are extremely small, etc. Servicing software must be rewritten A special window for operation with MWPC only has to be created, to not mix with many other tasks of SB. It must be well defined, what to be there. FE-channels have mistake in numbering (ch2 instead of ch1) according to CERN definition Thresholds must be separated at least for Wire and Cathode, and must be the simplest way to correct some thresholds by direct and random addressing via look_up_table of parameters. The software must operate in register units to be not depended on calibration… The units mV, fC at present version are wrong. Does not accept any rate window (only 1 and 10ms) Must allow threshold scan at various rate windows for wires and cathodes. All standard set of histogram characteristics has to be calculated (entries, mean, rms, fit by Gaussian, etc.) at the end of the threshold scan procedure and move to file Note: FWHM of the Gaussian fit gives Cdet: important for diagnostics. Q: Why so long time is spent for TH-scan: rate window 1-10ms x 224 channels = sec; in reality 11 minutes independently at any rate window? Q: What these messages mean ? I do not see anything bad in histo’s. –BAD CHANNEL node_id=60 i2c_ch=1 fe_addr=3 channel=3 Operator must decides ‘good or bad’ ALARM has to be specified and enabled by operator. Change manipulations with Excel-files within program: rather stupid situation at present - impossible use Excel in parallel. It must be clear for understanding: thershold, width of pulse; delay of pulse, logic, etc. (LUT gives this possibility: board by board) Threshold must be scan once (at present each time), then only ‘set’ using LUT in direct/random access, where only needed, if parameter is modified The software must more clearly write/read and show the data to/from DIALOG chip for information/modification, if operator decides do that. SB does not recognize FEB address (right side) if no LV on the neighbor branch (Left side). To localize only one FEB on one branch another must have LV and missing I2C terminators Impossible to set different thresholds for wire and cathode (e.g. M3R2) Provides instability in DCRO (e.g. M3R1)