Address alignment When a word (4-bytes) is loaded or stored the memory address must be a multiple of four. This is called an alignment restriction. Addresses that are a multiple of four are called word aligned (start with 0,4,8,C). General Purpose Register Not word aligned What looks like the binary address rightmost part for word aligned addresses ?

Endianness  A load word or store word instruction uses only one memory address.  The lowest address of the four bytes is used for the address of a block of four contiguous bytes.  How is a 32-bit pattern held in the four bytes of memory?  A choice has to be made about which byte of memory gets what part of the pattern.  There are two ways that computers commonly do this:  A load word or store word instruction uses only one memory address.  The lowest address of the four bytes is used for the address of a block of four contiguous bytes.  How is a 32-bit pattern held in the four bytes of memory?  A choice has to be made about which byte of memory gets what part of the pattern.  There are two ways that computers commonly do this: General Purpose Register

Big Endian and Little Endian  Big Endian Byte Order: The most significant byte (the "big end") of the data is placed at the lowest addressed byte.  Little Endian Byte Order: The least significant byte (the "little end") of the data is placed at the lowest addressed byte.  Big Endian Byte Order: The most significant byte (the "big end") of the data is placed at the lowest addressed byte.  Little Endian Byte Order: The least significant byte (the "little end") of the data is placed at the lowest addressed byte General Purpose Register Big Endian Order

 Say that the 32-bit pattern 0x is at address 0x  The most significant byte is 0x12;  the least significant is 0x78.  Here are the two byte orders: Big, Little endian example Lowest Address The Most Significant byte This is memory, not registers

 Within a byte, for all processors, bit 7 is the most significant bit.  So the big end byte looks the same for both byte orderings. Usually in printed material this bit is shown at the left, as in Bit Order

Byte Order of MIPS and SPIM Intel 80x86: little-endian processor family Macintosh OS runs on computers based on big-endian processors. IBM z/Architecture – Big endian More and more architectures use Bi-Endian hardware Allow switchable endianness ARM versions 3 and above, PowerPC,, SPARC V9, MIPS PA-RISC, SuperH SH-4 and IA-64, Alpha The SPIM simulator uses the byte ordering of the computer it is running on.

Load Word lw $10 $ opcode base dest offset lw $8, 0x60($10) The instruction immediately after a lw instruction should not use the register that is being loaded Which type of instruction is this ?

Store Word Instruction

 A MIPS halfword is two bytes.  Halfword addresses must be halfword aligned.  Attempting to load a halfword from an unaligned address will cause a trap. Loading Halfwords

Address alignment for halfword When a halfword (2-bytes) is loaded or stored the memory address must be a multiple of 2. Addresses that are a multiple of 2 are called halfword aligned (start with 0,2,4,…). General Purpose Register What looks like the binary address rightmost part for halfword aligned addresses ?

Storing Halfwords