Power Line Communication for Hybrid Power/Signal Pin SOC Design CK Cheng CSE Dept, UC San Diego

Page  2 Executive Summary

Page  3 Related Work  3D die-stacked technology [Ahn2014] [Chen2012]  Package on Package (POP) [Yoshida2006]  Coupled Communication [Hopkins2014]  Emerging Technologies [Hendry2014]  Power Transmission Line [Engin2008]  Switchable Pins with external switches [Chen2014] Our Proposed PLC 1.No requirement for advanced technology in PCB/PKG/DIE design 2.Minimal modifications to existing system design 3.No additional discrete component on PCB/PKG

Page  4 Design Overview  PLC Target: High current voltage domain pins, such as CPU, GPU, etc

Page  5 On-chip Implementation

Page  6 Package Implementation Original PKG Modified PKG for PLC

Page  7 PCB Implementation

Page  8 Signal Integrity Investigation  Sdd21: Differential forward gain from P3, P4 to P1 and P2 –Middle Notch Effect –Side Notch Effect  Simulation Setup: Mentor Expedition, Ansys Siwave and HFSS 2014, Sigrity and ADS on an Intel Xeon W3550 with 20GB DDR3

Page  9 Middle Notch Effect  Reducing middle notch length b. b w

Page  10 Middle Notch Effect b w Caseb (mm) (a) GHz4.104GHz (b) GHz6.506GHz (c) GHz9.910GHz (d) GHz12.51GHz

Page  11 Side Notch Effect  Tuning –side notch length –the distance from the edge of the side notch to the center of the middle notch ad

Page  12 Side Notch Effect Cased (mm) GHz34.13GHz GHz38.75GHz GHz41.74GHz Layout (0) Layout (1) Layout (3) Layout (4) Layout (5) Layout (2)

Page  13 PDN Investigation- PCB No notch Layout (0) Layout (1) Layout (2) Layout (3) Layout (4) Layout (5) P3 PDN Impedance at 100MHz P3 No notch Layout (0) Layout (1) Layout (2) Layout (3) Layout (4) Layout (5)

Page  14 Material Effect

Page  15 System Level Noise Mitigation Analysis The max coupling noise at each probe point 0.01uF decap placement location PLC: Assume 1Vdiff Input

Page  16 PDN Investigation- PKG Planes for Hybrid Pair 1 Planes for Hybrid Pair 2 Via to bumps Via to balls Planes for dedicated PWR Notches on PKG

Page  17 Case Study: A Complete Power Delivery and Data Communication Path PLC Data Channel PCB (Layout (1)) PKG Off-chip Driver SOC Receiver Differential forward transmission gain

Page  18 Eye 20GHz +V th -V th  The receiver uses simple peak- detectors and latch to regenerate the signal back to the original waveform. Driver Receiver

Page  19 Power Supply Noise Caused by PLC Voltage noise at the dedicated power pins (P5-P9).

Page  20 PDN (Impedance Profile) Measurement Setup Original PDN w/o hybrid pins: Modified PDN with one pair of hybrid pins and notches: VRM Original PCB Original PKG Die VRM Modifie d PKG Modified PCB On-die PWR Switch Die

Page  21 Impedance profile (Measured at the Die)

Page  22 Executive Summary

Page  23 PLC application at Modern SOC pinmap Green: GND Brown: VDD Top layer

Page  24 Layer 2

Page  25 Layer 3

Page  26 Layer 5

Page  27 Bottom Layer

Page  28 Layout Case 9 Transfer function

Page  29 Layout 9 Eye CH1 (25GHz) without decap  Noise

Page  30 Layout 9 Eye CH2 (25GHz) without decap Noise

Page  31 Layout 9 Eye CH2 (25GHz) with 220pF decap at each dedicated power pin Noise

Page  32 Layout 8

Page  33 Layout 6

Page  34 Layout 3

Page  35 PDN measurement  Setup

Page  36 Layout 11

Page  37 Layout 11 25GHz time domain CH1 and CH2 CH1CH2

Page  38 Layout 11 PDN

Page  39 Layout 10

Page  40 Layout 10 25GHz time domain CH1 and CH2 CH1CH2

Page  41 Layout 10 PDN

Page  42 Layout 10 vs 11 Complete PDN path (0.47uF brd cap)

Page  43 Layout 10 vs 11 Complete PDN path (2.2uF brd cap)

Page  44

Page  45 Q & A