ECFA Workshop, Warsaw, June G. Eckerlin Data Acquisition for the ILD G. Eckerlin ILD Meeting ILC ECFA Workshop, Warsaw, June 11 th 2008 DAQ Concept Current DAQ R&D Towards the LOI

ECFA Workshop, Warsaw, June G. Eckerlin The DAQ Concept readout between trains ~ 200 ms commercial hardware VTXSITFDT ECAL TPC HCAL PPPPPPPPPPPP Computing ressources (storage & analysis farm) Event building Network Event manager & Control Gb Links ~ 10 9 channels no hardware trigger 1 ms pipeline software event selection full train data to 1 node full detector information full train information -> flexible & efficient General concept unchanged since Tesla TDR

ECFA Workshop, Warsaw, June G. Eckerlin DAQ Architecture Preampli Shaper Digitizer VTX CCD MAPS DEPFET ….. TRK Si TPC ECAL Si W Scint W HCAL Digital Analog Muon RPC Scint … VFD Sensor technology FPGA Receiver Digital Processing MUX RO Buffer Local Data Management GDNGDN Local/Global Controls & Services Partition Running mode (Stand alone, test, RUN) Synchronization & machine interface Databases : Calibration & Monitoring …… On detector Very Front End Local Signal Processing and buffer Common/uniform Interface Front End (On / Near detector) Commercial standard Dedicated ASIC and/or SOC* Read Out Node/Hub *System On Chip Global Detector Network P. LeDu

ECFA Workshop, Warsaw, June G. Eckerlin Status of DAQ R&D Thanks to R&D collabrations quite some progress on Front end readout electronics on or near the detector (presentations from SiLC, LCTPC, CALICE/EUDET in the DAQ session) But also an ‘ILC like’ test beam DAQ design now (EUDET) Take EUDET/CALICE as an example On detector ASIC with shaping, sampling, digitizing, hit detection Near detector electronics for data collection, clock distribution, etc Off detector electronics and DAQ software

ECFA Workshop, Warsaw, June G. Eckerlin ILC Calorimeter DAQ (Valeria Bartsch) ILC Calorimetry will use particle flow algorithms to improve energy resolution => 1cmx1cm segmentation results in 100M channels with little room for electronics or cooling Bunch structure interesting: – ~200ms gaps between bunch- trains – Trains 1ms long, 300ns bunch spacing Triggerless => ~250 GB of raw data per bunch train need to be handled Time structure of bunches Trains of bunches Individual bunches M. Anduze “Final” Detector ECAL HCAL 1 st ECAL Module (module 0)

ECFA Workshop, Warsaw, June G. Eckerlin DAQ Architecture of CALICE/EUDET LDA Host PC PCIe ODR Host PC PCIe ODR Detector Unit DIF C&C Detector Unit DIF Detector Unit DIF Detector Unit DIF Storage 1-3Gb Fibre Mbps HDMI cabling m 0.1-1m Detector Counting Room Presented by Tao Wu Presented by Valeria Bartsch

ECFA Workshop, Warsaw, June G. Eckerlin CALICE DAQ architecture (Valeria Bartsch) Link Data Aggregator (LDA) Detector Interface (DIF) Detector Unit Off Detector Receiver (ODR) DAQ software Preparing for the technical prototype within EUDET in 2009

ECFA Workshop, Warsaw, June G. Eckerlin Off detector DAQ of CALICE (Tao Wu) Host PC PCIe ODR Host PC PCIe ODR C&C Storage 1-3Gb Fibre m Counting Room covered in Tao’s talk Data transfer from ODR to user program (memory) at ~ 700 MByte/sec Clock & Control board is designed will be built soon

ECFA Workshop, Warsaw, June G. Eckerlin EUDET DAQ will use DOOCS (Tao Wu) Software development and code base Computer Infrastructure Device layer Middle layer Communication Application layer Sun/Linux Cluster Software Libs The Distributed Object Oriented Control System will also be used for XFEL Control and DAQ.

ECFA Workshop, Warsaw, June G. Eckerlin May also learn from XFEL how to use xTCA K. Rehlich at the workshop on XFEL DAQ and Control for photon beam systems 2d pixel detectors for photon science have similar data rates. Large Pixel Detector : (by J Coughlan/RAL) 512 FEM with 10 Hz -> 150GB/sec

ECFA Workshop, Warsaw, June G. Eckerlin Towards LOI and beyond Too early for a full data model, but need to learn how to profit best from new technologies ( like ATCA/  TCA/AMC ) need event building for test systems with ‘ILC like architecture’ need to define standards and common interfaces for different detectors need to think about online data formats (offline software expects LCIO) good example : EUDET (FP6) ! maybe DEVDET (FP7) ? Newly developed test beam readout getting closer to reality make sure the readout interfaces do not diverge encourage all R&D groups to use a common interface address further common issues (calibration, commissioning, detector ctrl)

ECFA Workshop, Warsaw, June G. Eckerlin Thank you !

ECFA Workshop, Warsaw, June G. Eckerlin Some more examples of R&D Work

ECFA Workshop, Warsaw, June G. Eckerlin LC TPC Testbeam DAQ (X. Janssen)

ECFA Workshop, Warsaw, June G. Eckerlin Front End R&D Examples Architecture of CMOS readout chip of Silicon Strips (A. Savoy-Navarro for SiLC in the tracking session) New ASIC readout chip for analog HCAL tests (F. Sefkow for CALICE in the Calorimeter session) Many designs now fully integrate shaping, digitizing, hit detection, processing and digital buffering. Getting closer to a real design for the ILC operation. Output mostly digital via serial links (LVDS)