Indium Phosphide and Related Materials - 2006 Selectively implanted subcollector DHBTs Navin Parthasarathy, Z. Griffith, C. Kadow, U. Singisetti, and M.J.W. Rodwell Dept. of Electrical and Computer Engineering, University of California, Santa Barbara, CA M. Urteaga, K. Shinohara, B. Brar Rockwell Scientific Company, Thousand Oaks, CA Many thanks to the session chair and I wish to thank the program committee and everyone present. My name is Navin and I shall present the work done at UCSB on InP HBTs with implanted collectors. This work was supported under the DARPA-TFAST program

InP HBTs: solutions towards the future Outline Motivation InP HBTs: solutions towards the future Implanted Subcollector HBTs Pedestal-Subcollector HBTs Conclusions Since there were a number of excellent talks about InP HBTs, I shall run through the motivation behind this work and limitations with current InP mesa HBTs. I shall discuss the solutions being pursued at UCSB for scaling HBTs using implants.

Why are fast transistors required? Fiber Optic Communication Systems 40 Gb/s commercially available 80 and 160 Gb/s(?) long haul links High speed Instrumention mixed-signal ICs with large dynamic range mm-Wave Wireless Transmission high frequency communication links, atmospheric sensing, military and commercial radar Having said that “Why do we need fast transistors?” They find application in Fiber optic communication systems. They are used in mixed signal ICs for high speed instrumentation Mm-wave wireless circuitry requires fast transistors for communication links and sensing……… Fast Transistors…

Some common figures of merit ft is the unity current gain frequency fmax is the power gain cut-off frequency Digital delay not well correlated with tF (VLOGIC/Ic) (Ccb) is a major delay can be benchmarked using certain figures of merit. As you can see, ft at today’s scaling node, critically depends on the collector and base transit time while fmax depends on Ccb and Rbb….Ft and fmax are analog figures of merit. It is seen that digital delay does not correlate well with ft. Working thro the charging time constants, it is seen that Ccb times delta VL over Ic is the major delay. VL is set by the thermal noise margin of the differential pair and therefore Ccb / I must be reduced. Scaling Ccb is not easy this serves as the motivation for this work Collector Base capacitance must be reduced

InP vs Si/SiGe HBTs Scaling Laws for HBTs InP system has inherent material advantages over Si/SiGe 20x lower base sheet resistance, 5x higher electron velocity, 4x higher breakdown-at same ft. but… today’s SiGe HBTs are fast catching up due to 5x smaller scaling and offer much higher levels of integration due to the Si platform Scaling Laws for HBTs So Why are InP HBTs fast It boast of 20 times lower base sheet resistance, 5 times greater electron velocity and more breakdown at same ft. However todays SiGe HBTs are almost as fast as InP HBTs owing to the smaller scaling and offers greater integration due to the highly advanced Si processing technology. So we need to scale and how..? Reduce vertical dimensions to decrease transit times Reduce lateral dimensions to decrease RC time constants Increase current density to decrease charging time However, Reduce vertical dimensions to decrease transit times Reduce lateral dimensions to decrease RC time constants Increase current density to decrease charging time

InP HBTs today… and tomorrow? A Radical approach is necessary Parasitic base collector capacitance under base contacts Base ohmic transfer length limits collector scaling Non-planar device E B C Key Challenges for InP HBTs Scaling of collector-base junction Planar, manufacturable process for high levels of integration Narrow base-emitter junction formation and also low Rex there are several limitations to such scaling imposed by the mesa HBT structure. The base contacts should be at least one ohmic transfer length limiting collector scaling, and there is a parasitic capacitance associated with the base access pad and the non-planar geometry results in low yield.. Several challenges lay ahead to realize the fill potential of InP HBTs. Foremost is the scaling of the collector base junction. A Radical approach is necessary

The end goal: SiGe-like highly scaled InP HBT Regrown submicron emitter submicron emitter scaling: speed large emitter contact: low Rex, speed Objectives: Extreme parasitic reduction: speed Planar Geometry: yield Extrinsic base thick extrinsic base: low Rbb, speed Emitter contact Base contact Emitter Extrinsic base Intrinsic base Collector contact N++ pedestal N- collector Combining the best features of SiGe HBT technology, we propose the ultimately scaled InP HBT. We seek extreme parasitic reduction and a planar geometry It features an implant isolated subcollector for zero base pad capacitance and hence larger contact pads Pedestal collector which enables submicron collector scaling, 1 sided collector contact for reduced device dimensions A thick extrinsic base…. Regrown submicron emitter for highly scaled emitter-base junction with simultaneously large emitter contacts. And, all this while maintaining a planar geometry. How do we make a super HBT?...We attacked it in a modular fashion and today I shall discuss only modules 1 and 2 on collector scaling Pedestal collector submicron collector scaling: speed One sided collector : integration Isolated subcollector MODULE 2 Isolated subcollector large base pad: yield zero base pad capacitance: speed MODULE 1

The end goal: SiGe-like highly scaled InP HBT Emitter contact Base contact Emitter Extrinsic base Intrinsic base Collector contact N++ pedestal N- collector We shall start with isolating the subcollector first. Isolated subcollector Isolated subcollector zero base pad capacitance: speed MODULE 1

Module 1: Access Pad Capacitance in InP HBTs Subcollector boundary Parasitic Base access pad 0.6μm DHBT fabricated at UCSB Ccb, pad ~30% of overall Ccb Increasingly significant for short emitter lengths In modern mesa HBTs, there is this base access pad to contact the base of the HBT. This contributes to collector base capacitance. Shorter length devices are used for low power high speed logic. But the pad capacitance starts to become significant a shorter lengths. The simplest….approach to eliminate the pad capacitance is to have an N+ subcollector only in the active device area, so that the base pad lies on SI InP. IMPORTANT FOR FAST, LOW POWER LOGIC

Implanted subcollector InP DHBTs Implanted N++ InP subcollector Collector contact Emitter contact N- collector SI substrate Approach Selectively implanted N++ subcollector Growth of drift collector, base & emitter Device formation Interface charge compensation N++ charge present on exposed InP surface Fe implant suppresses interface charge Side View And..how is this done? Selectively implanting Si to form an N++ subcollector. This is then just followed by regular growth starting with the drift collector. However InP growth surfaces have a classic problem. An N+ interface charge is present on all exposed InP surfaces. Now this charge is present under the base pad and is a terminating dipole for the base collector electric field. Therefore the capacitance under here will not be eliminated unless this charge gets depleted,……. or suppressed. Various process techniques but we used the power of implants…by compensating this charge with Fe which is a mid gap acceptor. So with these 2 implants…what

Implanted subcollector DHBT with Fe : The Process Anneal Anneal and MBE growth Device formation So with these 2 implants, what does the process flow look like? Implant Iron shallow everywhere, Anneal the wafer and the selectively implant Si only for the active device part. Activate the Si and then grown the collector, base and emitter stack. In this dark blue region, the subcollector, the Si implant is designed to overcome the surface Fe…. Therefore the device here is identical to a standard mesa device and…DC

Implanted subcollector DHBTs with Fe – DC results DC characteristics - Gain, Ideality factors, Leakage currents…are similar to fully epitaxial device The DC results do confirm that….the gain, ideality factors, offset voltage, and low leakage current are similar to what is obtained for a fully epitaxial device. Peak   35, BVCBO = 5.31V (Ic=50 A) Base (from TLM) : Rsheet = 1050 /sq, Rcont = 50 m2 Collector (from TLM) : Rsheet ~ 25.0 /sq, Rcont ~ 110 m

Implanted subcollector DHBTs with Fe – RF results fτ = 363 GHz, fmax = 410 GHz The acid test is the Capacitance measurement. Comparing with an identical standard mesa device, the implanted subcollector DHBT with Fe has reduced Ccb over the entire bias range by ~ 3fF, which corresponds to the elimination of the base pad capacitance. What about RF performance, these devices have yielded fast DHBTs with cut off frequencies of around 400GHz. With one part complete… Ccb reduced by ~ 25 %

Module 2: Submicron collector scaling Emitter contact Base contact Emitter Extrinsic base Intrinsic base Collector contact N++ pedestal N- collector Pedestal collector submicron collector scaling: speed We now desire more collector scaling. Extending the idea of using Fe and Si implants for the implanted subcollector DHBTs, we propose Isolated subcollector MODULE 2 Isolated subcollector large base pad: yield zero base pad capacitance: speed MODULE 1

An elegant approach to collector scaling The triple implanted subcollector-pedestal HBT deep N++ InP subcollector by selective Si implant → isolate base pad (Module 1) 2. SI layer ~0.2μm, by Fe implant → decrease extrinsic Ccb 3. Second Si implant creates N++ pedestal for current flow 4. Growth of drift collector, base & emitter and device formation Fe implanted current block Collector contact N- collector N+ pedestal N+ InP sub-collector SI InP substrate A novel approach to collector scaling. form an N++ subcollector by deep Si implant. implant the top 0.2um with Fe to make it intrinsic. then add N+ channels to link to the subcollector. And then as before, is just regular growth. As you can see, the current flow is vertical, the capacitance in the extrinsic region is reduced due to the larger depletion width here. And there are several advantages to this technique…. Subcollector boundary Pedestal implant N. Parthasarathy et al., Electron Device Letters, Vol. 27(5), May 06

Fe implanted current block An elegant approach to collector scaling The triple implanted subcollector-pedestal HBT Advantages over standard mesa device Fe implanted current block Collector Base junction can be independently scaled Pad capacitance eliminated Increased Breakdown voltages N+ pedestal N- collector N+ InP sub-collector SI InP substrate More benefits…. 4. Highly planar, fully implanted process, no regrowth required → manufacturability 5. Implants before growth endless variations in subcollector-pedestal layers without compromising device planarity 6. Fe compensates interface charge → reliability and repeatability Independent collector scaling Since the subcollector is selectively implanted, the pad cap is eliminated And there is an increase in the breakdown voltage due to lower surface conduction. More importantly it does not require any regrowth and is cheap and manufacturable. It is modular and can be added to anyone’s process. Implants offer endless design possibilities. Most elegantly, the Fe implant automatically compensates interface charge

RF performance: fully implanted subcollector-pedestal HBT Ccb reduced by ~ 50% fτ = 352 GHz, fmax = 403 GHz …to the device results. As seen, Ccb is reduced by ~50% and the RF performance of this first time demonstration, make this the fastest implanted DHBT ever built. N. Parthasarathy et al., Electron Device Letters, May 06

-Kroemer’s Lemma of New Technology Conclusion Implanted collector InP HBTs at 500 nm scaling generation ~ 400 GHz ft & fmax Implanted subcollector DHBTs – eliminate pad capacitance Implanted pedestal-subcollector DHBTs – independent collector scaling InP HBT future: 125 nm scaling generation with implanted pedestal-subcollectors ~1 THz ft & fmax, 400 GHz digital latches & 600 GHz amplifiers? Applications 160+ Gb/s fiber ICs, 300 GHz MMICs for communications, radar, & imaging & applications unforeseen & unanticipated “The principal applications of any sufficiently new and innovative technology always have been – and will continue to be – applications created by that technology.” -Kroemer’s Lemma of New Technology So…..what do all these mean. These implanted InP HBTs have achieved Ccb reduction of over 25% and in the process are the fastest implanted DHBTs ever. Tomorrows 125nm devices with these enhancements should make possible digital logic at over 400GHz and cut off frequencies of a THz These might find applications in 160Gb/s chip sets, high bandwidth MMICs and may create new applications. Indeed…