CS141-L4-1Tarun Soni, Summer’03 Single Cycle CPU  Previously: built and ALU.  Today: Actually build a CPU Questions on CS140 ? Computer Arithmetic ? Attend office hours with TAs or me. Do the exercises in the text.

CS141-L4-2Tarun Soni, Summer’03  Instruction Set Architectures  Performance issues  2s complement, Addition, Subtraction  Multiplication, Division, Floating Point numbers The Story so far: Basically ISA & ALU stuff

CS141-L4-3Tarun Soni, Summer’03 CPU: Building blocks Adder MUX ALU 32 A B Sum Carry 32 A B Result OP 32 A B Y Select Adder MUX ALU CarryIn

CS141-L4-4Tarun Soni, Summer’03 CPU: Building blocks OP 32 A B Y Select MUX 32 A[31..0] B[31..0] 32 Sum[31..0] Carry Adder CarryIn 32 A[63..32] B[63..32] 32 Sum[63..32] Carry Adder CarryIn 32 Building a 64-bit adder from 2x32-bit adders

CS141-L4-5Tarun Soni, Summer’03 CPU: Building blocks 32 A B Sum[63..32] 32 Select MUX 32 A[31..0] B[31..0] 32 Sum[31..0] Carry Adder CarryIn 32 A[63..32] B[63..32] 32 S Cout Adder Cin=0 32 A[63..32] B[63..32] 32 S Cout Adder Cin=1 1 A B 1 Cout 1 Select MUX Silicon is cheap – sort-of

CS141-L4-6Tarun Soni, Summer’03 CPU Single Cycle CPU

CS141-L4-7Tarun Soni, Summer’03 CPU The Big Picture: Where are We Now? The Five Classic Components of a Computer Datapath Design, then Control Design Control Datapath Memory Processor Input Output

CS141-L4-8Tarun Soni, Summer’03 CPU: The big picture Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction ° Design hardware for each of these steps!!! Execute an entire instruction FetchDecode Fetch Execute Store Next

CS141-L4-9Tarun Soni, Summer’03 CPU: Clocking Clk Don’t Care SetupHold SetupHold All storage elements are clocked by the same clock edge

CS141-L4-10Tarun Soni, Summer’03 CPU The Big Picture: The Performance Perspective Execution Time = Insts * CPI * Cycle Time Processor design (datapath and control) will determine: –Clock cycle time –Clock cycles per instruction Starting today: –Single cycle processor: Advantage: One clock cycle per instruction Disadvantage: long cycle time Execute an entire instruction

CS141-L4-11Tarun Soni, Summer’03 CPU We're ready to look at an implementation of the MIPS Simplified to contain only: –memory-reference instructions: lw, sw –arithmetic-logical instructions: add, sub, and, or, slt –control flow instructions: beq Generic Implementation: –use the program counter (PC) to supply instruction address –get the instruction from memory –read registers –use the instruction to decide exactly what to do All instructions use the ALU after reading the registers memory-reference? arithmetic? control flow? CPI Inst. CountCycle Time

CS141-L4-12Tarun Soni, Summer’03 CPU Review: The MIPS Instruction Formats optarget address bits26 bits oprsrtrdshamtfunct bits 5 bits oprsrt immediate bits16 bits5 bits °The different fields are: op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of the jump instruction

CS141-L4-13Tarun Soni, Summer’03 CPU R-type –add rd, rs, rt –sub, and, or, slt LOAD and STORE –lw rt, rs, imm16 –sw rt, rs, imm16 BRANCH: –beq rs, rt, imm16 oprsrtrdshamtfunct bits 5 bits oprsrtimmediate bits16 bits5 bits oprsrtdisplacement bits16 bits5 bits

CS141-L4-14Tarun Soni, Summer’03 CPU Memory –instruction & data Registers (32 x 32) –read RS –read RT –Write RT or RD PC Extender Add and Sub register or extended immediate Add 4 or extended immediate to PC Requirements to implement the ISA

CS141-L4-15Tarun Soni, Summer’03 CPU Combinational Elements Storage Elements –Clocking methodology State Element clk A B C = f(A,B,state) {State[n] = f(A,B,state[n-1])} Combinational Logic A B C = f(A,B)

CS141-L4-16Tarun Soni, Summer’03 CPU: Storage unit The set-reset latch –output depends on present inputs and also on past inputs

CS141-L4-17Tarun Soni, Summer’03 CPU: D-flip flop Two inputs: –the data value to be stored (D) –the clock signal (C) indicating when to read & store D Two outputs: –the value of the internal state (Q) and it's complement Output changes only on the clock edge

CS141-L4-18Tarun Soni, Summer’03 CPU: Clocking Methodology An edge triggered methodology Typical execution: –read contents of some state elements, –send values through some combinational logic –write results to one or more state elements

CS141-L4-19Tarun Soni, Summer’03 CPU: Storage block Register –Similar to the D Flip Flop except N-bit input and output Write Enable input –Write Enable: 0: Data Out will not change 1: Data Out will become Data In (on the clock edge) Clk Data In Write Enable NN Data Out

CS141-L4-20Tarun Soni, Summer’03 CPU: Register Files Register File consists of (32) registers: –Two 32-bit output buses: –One 32-bit input bus: busW Register is selected by: –RA selects the register to put on busA –RB selects the register to put on busB –RW selects the register to be written via busW when Write Enable is 1 Clock input (CLK) Factor only during write-enable=1; Otherwise, this unit acts just like combinational logic. Clk busW Write Enable 32 busA 32 busB 555 RWRARB bit Registers

CS141-L4-21Tarun Soni, Summer’03 CPU: Register Files Built using D-flip flops Still use the real clock (not shown here) to do the actual write

CS141-L4-22Tarun Soni, Summer’03 CPU: Memory Memory (idealized) –One input bus: Data In –One output bus: Data Out Memory word is selected by: –Address selects the word to put on Data Out –Write Enable = 1: address selects the memory word to be written via the Data In bus Clock input (CLK) –The CLK input is a factor ONLY during write operation –During read operation, behaves as a combinational logic block: Address valid => Data Out valid after “access time.” Clk Data In Write Enable 32 DataOut Address

CS141-L4-23Tarun Soni, Summer’03 CPU: RTL is a mechanism for describing the movement and manipulation of data between storage elements: R[3] <- R[5] + R[7] PC <- PC R[5] R[rd] <- R[rs] + R[rt] R[rt] <- Mem[R[rs] + immed] Register Transfer Language (RTL)

CS141-L4-24Tarun Soni, Summer’03 CPU: More building blocks

CS141-L4-25Tarun Soni, Summer’03 CPU: The big picture Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction ° Design hardware for each of these steps!!! Execute an entire instruction FetchDecode Fetch Execute Store Next

CS141-L4-26Tarun Soni, Summer’03 CPU: Instruction Fetch RTL version of the instruction fetch step: Fetch the Instruction: mem[PC] –Update the program counter: Sequential Code: PC <- PC + 4 Branch and Jump: PC <- “something else” 32 Instruction Word Address Instruction Memory PC Clk Next Address Logic

CS141-L4-27Tarun Soni, Summer’03 CPU: Binary arithmetic for PC In theory, the PC is a 32-bit byte address into the instruction memory: –Sequential operation: PC = PC + 4 –Branch operation: PC = PC SignExt[Imm16] * 4 The magic number “4” always comes up because: –The 32-bit PC is a byte address –And all our instructions are 4 bytes (32 bits) long In other words: –The 2 LSBs of the 32-bit PC are always zeros –There is no reason to have hardware to keep the 2 LSBs In practice, we can simplify the hardware by using a 30-bit PC : –Sequential operation: PC = PC + 1 –Branch operation: PC = PC SignExt[Imm16] –In either case: Instruction Memory Address = PC concat “00”

CS141-L4-28Tarun Soni, Summer’03 CPU: Instruction Fetch unit The common RTL operations –Fetch the Instruction: inst <- mem[PC] –Update the program counter: Sequential Code: PC <- PC + 4 Branch and Jump PC <- “something else”

CS141-L4-29Tarun Soni, Summer’03 CPU: Register-Register Operations (Add, Subtract etc.) R[rd] <- R[rs] op R[rt] Example: addU rd, rs, rt –Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields –ALUctr and RegWr: control logic after decoding the instruction 3232 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers RsRtRd ALU oprsrtrdshamtfunct bits 5 bits ° Worry about instruction decode to generate ALUctr and RegWr later.

CS141-L4-30Tarun Soni, Summer’03 CPU: Register - Register Timing 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers RsRtRd ALU Clk PC Rs, Rt, Rd, Op, Func Clk-to-Q ALUct r Instruction Memory Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA, B Register File Access Time Old ValueNew Value busW ALU Delay Old ValueNew Value Old ValueNew Value Old Value Register Write Occurs Here

CS141-L4-31Tarun Soni, Summer’03 CPU: Logical Immediate Op. R[rt] <- R[rs] op ZeroExt[imm16] ] 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs RtRd RegDst ZeroExt Mux imm16 ALUSrc ALU 11 oprsrtimmediate bits16 bits5 bits rd? immediate bits Handle Rt as destination Handle Immediate as operand

CS141-L4-32Tarun Soni, Summer’03 CPU: Load Operations R[rt] <- Mem[R[rs] + SignExt[imm16]]Example: lw rt, rs, imm16 11 oprsrtimmediate bits16 bits5 bits rd 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs RtRd RegDst Extender Mux imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory 32 ALU MemWr Mu x W_Src Need data Memory! Reg-Write could be from result or data memory

CS141-L4-33Tarun Soni, Summer’03 CPU: Store Operations Mem[ R[rs] + SignExt[imm16] <- R[rt] ] Example: sw rt, rs, imm16 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst Extender Mux imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory MemWr ALU oprsrtimmediate bits16 bits5 bits 32 Mu x W_Src Reg can write to Data Memory

CS141-L4-34Tarun Soni, Summer’03 CPU: Branching beqrs, rt, imm16 –mem[PC]Fetch the instruction from memory –Equal <- R[rs] == R[rt]Calculate the branch condition –if (COND eq 0)Calculate the next instruction’s address PC <- PC ( SignExt(imm16) x 4 ) –else PC <- PC + 4 oprsrtimmediate bits16 bits5 bits

CS141-L4-35Tarun Soni, Summer’03 CPU: Datapath for Branching beq rs, rt, imm16Datapath generates condition (equal) oprsrtimmediate bits16 bits5 bits 32 imm16 PC Clk 00 Adder Mux Adder 4 nPC_sel Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Equal? Cond PC Ext Inst Address Calculate (PC+4) as well as (imm16+PC+4) and choose one Calculate the “condition” part of the branch op.

CS141-L4-36Tarun Soni, Summer’03 CPU: The Aggregate Datapath imm16 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst Extender Mux imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal Instruction Imm16RdRtRs = Adder PC Clk 00 Mux 4 nPC_sel PC Ext Adr Inst Memory Still need to worry about Instruction Decode

CS141-L4-37Tarun Soni, Summer’03 CPU: Datapath: High-level view Register file and ideal memory: –The CLK input is a factor ONLY during write operation –During read operation, behave as combinational logic: Address valid => Output valid after “access time.” Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew Clk 5 RwRaRb bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 16 Imm 32 A B Next Address

CS141-L4-38Tarun Soni, Summer’03 CPU: Control Signals ALUctr RegDst ALUSrc ExtOp MemtoRegMemWr Equal Instruction Imm16RdRsRt nPC_sel Adr Inst Memory DATA PATH Control Op Fun RegWr

CS141-L4-39Tarun Soni, Summer’03 CPU: Control Signals: Meaning Adr Inst Memory Rs, Rt, Rd and Imed16 hardwired into datapath nPC_sel: 0 => PC PC <– PC SignExt(Im16) || 00 Adder PC Clk 00 Mux 4 nPC_sel PC Ext imm16

CS141-L4-40Tarun Soni, Summer’03 CPU: Control Signals: Meaning ExtOp:“zero”, “sign” ALUsrc:0 => regB; 1 => immed ALUctr:“add”, “sub”, “or” 32 ALUct r Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst Extender Mux imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal °MemWr:write memory °MemtoReg:1 => Mem °RegDst:0 => “rt”; 1 => “rd” °RegWr:write dest register =

CS141-L4-41Tarun Soni, Summer’03 CPU: Control Signals for various operations inst Register Transfer ADDR[rd] <– R[rs] + R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4” SUBR[rd] <– R[rs] – R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4” ORiR[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4” LOADR[rt] <– MEM[ R[rs] + sign_ext(Imm16)];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4” STOREMEM[ R[rs] + sign_ext(Imm16)] <– R[rs];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4” BEQif ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = EQUAL, ALUctr = “sub”

CS141-L4-42Tarun Soni, Summer’03 CPU: Control Signals: Logic Design nPC_sel <= if (OP == BEQ) then EQUAL else 0 ALUsrc <=if (OP == “000000”) then “regB” else “immed” ALUctr<= if (OP == “000000”) then funct elseif (OP == ORi) then “OR” elseif (OP == BEQ) then “sub” else “add” ExtOp <= _____________ MemWr<= _____________ MemtoReg<= _____________ RegWr:<=_____________ RegDst:<= _____________

CS141-L4-43Tarun Soni, Summer’03 CPU: Control Signals: Logic Design nPC_sel <= if (OP == BEQ) then EQUAL else 0 ALUsrc <=if (OP == “000000”) then “regB” else “immed” ALUctr<= if (OP == “000000”) then funct elseif (OP == ORi) then “OR” elseif (OP == BEQ) then “sub” else “add” ExtOp <= if (OP == ORi) then “zero” else “sign” MemWr<= (OP == Store) MemtoReg<= (OP == Load) RegWr:<= if ((OP == Store) || (OP == BEQ)) then 0 else 1 RegDst:<= if ((OP == Load) || (OP == ORi)) then 0 else 1

CS141-L4-44Tarun Soni, Summer’03 CPU: Example: Load R[rt] <- Mem[R[rs] + SignExt[imm16]] Viz., lw rt, rs, imm16

CS141-L4-45Tarun Soni, Summer’03 CPU: The abstract version Logical vs. Physical Structure Data Out Clk 5 RwRaRb bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions

CS141-L4-46Tarun Soni, Summer’03 CPU: The real thing

CS141-L4-47Tarun Soni, Summer’03 CPU: 5 steps to design 5 steps to design a processor –1. Analyze instruction set => datapath requirements –2. Select set of datapath components & establish clock methodology –3. Assemble datapath meeting the requirements –4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. –5. Assemble the control logic MIPS makes it easier –Instructions same size –Source registers always in same place –Immediates same size, location –Operations always on registers/immediates Single cycle datapath => CPI=1, CCT => long

CS141-L4-48Tarun Soni, Summer’03 CPU: Control Section The Five Classic Components of a Computer Control Datapath Memory Processor Input Output

CS141-L4-49Tarun Soni, Summer’03 CPU: Add Instruction addrd, rs, rt –mem[PC]Fetch the instruction from memory –R[rd] <- R[rs] + R[rt]The actual operation –PC <- PC + 4Calculate the next instruction’s address oprsrtrdshamtfunct bits 5 bits

CS141-L4-50Tarun Soni, Summer’03 CPU: The Add Instruction Instruction Fetch Unit at the Beginning of Add PC Ext Fetch the instruction from Instruction memory: Instruction <- mem[PC] –This is the same for all instructions Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction

CS141-L4-51Tarun Soni, Summer’03 CPU: The Add Instruction The Single Cycle Datapath during Add 32 ALUctr = Add Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = 1 Extender Mux imm16 ALUSrc = 0 Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction R[rd] <- R[rs] + R[rt] Imm16RdRsRt oprsrtrdshamtfunct nPC_sel= +4

CS141-L4-52Tarun Soni, Summer’03 CPU: The Add Instruction Instruction Fetch Unit at the End of Add PC <- PC + 4 –This is the same for all instructions except: Branch and Jump Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction

CS141-L4-53Tarun Soni, Summer’03 CPU: The Or Immediate Instruction R[rt] <- R[rs] or ZeroExt[Imm16] oprsrtimmediate ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = Extender Mux imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt nPC_sel =

CS141-L4-54Tarun Soni, Summer’03 CPU: The Or Immediate Instruction The Single Cycle Datapath during Or Immediate 32 ALUctr = Or Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = 0 Extender Mux imm16 ALUSrc = 1 ExtOp = 0 Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction R[rt] <- R[rs] or ZeroExt[Imm16] Imm16RdRsRt oprsrtimmediate nPC_sel= +4

CS141-L4-55Tarun Soni, Summer’03 CPU: The Load Instruction The Single Cycle Datapath during Load 32 ALUctr = Add Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = 0 Extender Mux imm16 ALUSrc = 1 ExtOp = 1 Mux MemtoReg = 1 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt R[rt] <- Data Memory {R[rs] + SignExt[imm16]} oprsrtimmediate nPC_sel= +4

CS141-L4-56Tarun Soni, Summer’03 CPU: The Store Instruction The Single Cycle Datapath during Store Data Memory {R[rs] + SignExt[imm16]} <- R[rt] oprsrtimmediate ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = Extender Mux imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt nPC_sel =

CS141-L4-57Tarun Soni, Summer’03 CPU: The Store Instruction The Single Cycle Datapath during Store 32 ALUctr = Add Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = x Extender Mux imm16 ALUSrc = 1 ExtOp = 1 Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 1 ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt Data Memory {R[rs] + SignExt[imm16]} <- R[rt] oprsrtimmediate nPC_sel= +4

CS141-L4-58Tarun Soni, Summer’03 CPU: Datapath during branch 32 ALUctr = Subtract Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = x Extender Mux imm16 ALUSrc = 0 ExtOp = x Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0 oprsrtimmediate nPC_sel= “Br”

CS141-L4-59Tarun Soni, Summer’03 CPU: Datapath during branch Instruction Fetch Unit at the End of Branch if (Zero == 1) then PC = PC SignExt[imm16]*4 ; else PC = PC + 4 oprsrtimmediate Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction

CS141-L4-60Tarun Soni, Summer’03 CPU: Creating control from Datapath ALUctr RegDst ALUSrc ExtOp MemtoRegMemWr Equal Imm16RdRsRt nPC_sel Adr Inst Memory DATA PATH Control Op Fun RegWr

CS141-L4-61Tarun Soni, Summer’03 CPU: Control Signals inst Register Transfer ADDR[rd] <– R[rs] + R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4” SUBR[rd] <– R[rs] – R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4” ORiR[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4” LOADR[rt] <– MEM[ R[rs] + sign_ext(Imm16)];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4” STOREMEM[ R[rs] + sign_ext(Imm16)] <– R[rs];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4” BEQif ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = “Br”, ALUctr = “sub”

CS141-L4-62Tarun Soni, Summer’03 CPU: Summary of Control Signals addsuborilwswbeqjump RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr x Add x Subtract Or Add x 1 x x 0 x x Subtract x x x x xxx optarget address oprsrtrdshamtfunct oprsrt immediate R-type I-type J-type add, sub ori, lw, sw, beq jump func op Appendix A See We Don’t Care :-)

CS141-L4-63Tarun Soni, Summer’03 CPU: Summary of Control Signals The Concept of Local Decoding Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 ALU

CS141-L4-64Tarun Soni, Summer’03 CPU: Encoding of ALUop In this exercise, ALUop has to be 2 bits wide to represent: –(1) “R-type” instructions –“I-type” instructions that require the ALU to perform: (2) Or, (3) Add, and (4) Subtract To implement the full MIPS ISA, ALUop has to be 3 bits to represent: –(1) “R-type” instructions –“I-type” instructions that require the ALU to perform: (2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi) Main Control op 6 ALU Control (Local) funcN 6 ALUop ALUctr 3 R-typeorilwswbeqjump ALUop (Symbolic)“R-type”OrAdd Subtract xxx ALUop xxx

CS141-L4-65Tarun Soni, Summer’03 CPU: Decoding of the ‘func’ field R-typeorilwswbeqjump ALUop (Symbolic)“R-type”OrAdd Subtract xxx ALUop xxx Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 oprsrtrdshamtfunct R-type funct Instruction Operation add subtract and or set-on-less-than ALUctr ALU Operation Add Subtract And Or Set-on-less-than Recall ALUctr ALU

CS141-L4-66Tarun Soni, Summer’03 CPU: Truth table for ALUctr R-typeorilwswbeq ALUop (Symbolic) “R-type”OrAdd Subtract ALUop funct Instruction Op add subtract and or set-on-less-than

CS141-L4-67Tarun Soni, Summer’03 CPU: Logic Equation ALUctr[2] The Logic Equation for ALUctr ALUopfunc bit ALUctr 0x1xxxx1 1xx xx10101 ALUctr = !ALUop & ALUop + ALUop & !func & func & !func This makes func a don’t care

CS141-L4-68Tarun Soni, Summer’03 CPU: Logic Equation ALUctr[1] The Logic Equation for ALUctr ALUopfunc bit 000xxxx1 ALUctr 0x1xxxx1 1xx xx xx10101 ALUctr = !ALUop & !ALUop + ALUop & !func & !func

CS141-L4-69Tarun Soni, Summer’03 CPU: Logic Equation ALUctr[0] The Logic Equation for ALUctr ALUopfunc bit ALUctr 01xxxxx1 1xx xx10101 ALUctr = !ALUop & ALUop + ALUop & !func & func & !func & func + ALUop & func & !func & func & !func

CS141-L4-70Tarun Soni, Summer’03 CPU: ALU Control block The ALU Control Block ALU Control (Local) func 3 6 ALUop ALUctr 3 ALUctr = !ALUop & ALUop + ALUop & !func & func & !func ALUctr = !ALUop & !ALUop + ALUop & !func & !func ALUctr = !ALUop & ALUop + ALUop & !func & func & !func & func + ALUop & func & !func & func & !func

CS141-L4-71Tarun Soni, Summer’03 CPU: Main Control R-typeorilwswbeqjump RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop (Symbolic) x “R-type” Or Add x 1 x x 0 x x Subtract x x x x xxx op ALUop x x x Main Control op 6 ALU Control (Local) func 3 6 ALUop ALUctr 3 RegDst ALUSrc :

CS141-L4-72Tarun Soni, Summer’03 CPU: Main Control The “Truth Table” for RegWrite R-typeorilwswbeqjump RegWrite op RegWrite = R-type + ori + lw = !op & !op & !op & !op & !op & !op (R-type) + !op & !op & op & op & !op & op (ori) + op & !op & !op & !op & op & op (lw) RegWrite

CS141-L4-73Tarun Soni, Summer’03 CPU: Main Control PLA Implementation of the Main Control RegWrite ALUSrc MemtoReg MemWrite Branch Jump RegDst ExtOp ALUop

CS141-L4-74Tarun Soni, Summer’03 CPU Putting it All Together: A Single Cycle Processor 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst Extender Mux imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt Main Control op 6 ALU Control func 6 3 ALUop ALUctr 3 RegDst ALUSrc : Instr nPC_sel

CS141-L4-75Tarun Soni, Summer’03 CPU Worst Case Timing (Load) Clk PCPC Rs, Rt, Rd, Op, Func Clk-to-Q ALUct r Instruction Memoey Access Time Old ValueNew Value RegW r Old ValueNew Value Delay through Control Logic busA Register File Access Time Old ValueNew Value busB ALU Delay Old ValueNew Value Old ValueNew Value Old Value ExtOpOld ValueNew Value ALUSrcOld ValueNew Value MemtoRe g Old ValueNew Value Addre ss Old ValueNew Value busWOld ValueNew Delay through Extender & Mux Register Write Occurs Data Memory Access Time

CS141-L4-76Tarun Soni, Summer’03 CPU: Single Cycle Solution Long cycle time: –Cycle time must be long enough for the load instruction: PC’s Clock -to-Q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew Cycle time for load is much longer than needed for all other instructions

CS141-L4-77Tarun Soni, Summer’03 CPU: Single Cycle Solution °Single cycle datapath => CPI=1, CCT => long °5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic °Control is the hard part °MIPS makes control easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Control Datapath Memory Processor Input Output

CS141-L4-78Tarun Soni, Summer’03 CPU: Interrupts °Datapath for interrupts °Interrupt: basically hardware line requesting an immediate jump °PC = Int[I] if Int[I] = 1; °May or maynot save registers °May or maynot be maskable. °Useful for multitasking control & real-time processing °Signal Processing °Harder to implement in case of a multi-cycle/pipelines system !