Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 20: Cache Design Spring 2009 W. Rhett Davis NC State University with significant material from Paul Franzon, Bill Allen, & Xun Liu

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 2 Announcements l HW#8 Due Today l Proj#2 Due in 2 weeks l Exam Review in 2 weeks l Proj#2 Advising next Tuesday (in our regular classroom)

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 3 Mentor Moment l Keep the lines of communication open l How do you respond to your inbox? » My common mistake: –respond well » A much better approach: –respond quickly l Resist the urge to… » Use your inbox as a to-do list » Spend more than 2 minutes per message l My favorite time-management book:

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 4 Today’s Lecture l Project #2 Introduction

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 5 Project #1 System l Synchronous Memory with Separate din/dout/address lines

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 6 Project #2 Changes l Asynchronous Off-Chip Memory with Shared din/dout/address lines l Cache sits between processor and memory l LC3 Unchanged except for “macc” signal » High when state is Fetch, Read Memory, Write Memory, or Read Indirect Address l SimpleLC3 and Memory blocks will be provided

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 7 Data Transfer Interface Cache Off-chip Memory Read request (rrqst) Data/Address(data) Read ready(rrdy) Read data ready(rdrdy) Read data accept(rdacpt) Write request(wrqst) Write accept(wacpt) addr din rd dout complete clock reset Memory Access (macc)

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 8 Protocol for Read Miss addressdata0data1data2data3 Read request Read ready Read data ready Read data accept

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 9 Protocol for Write Hit addressdata Write request Write accept

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 10 Protocol for Write Miss Read request addrdata data0data1data2data3 Read data ready Read data accept Write reqst Write acpt data

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 11 Cache System Block-Diagram

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 12 UnifiedCache Schematic

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 13 CacheController Block l Takes the handshaking signals from the LC-3 CPU and Off-Chip Memory as inputs l Takes miss indicator from CacheData as input l Maintains the state of the Cache and Interfaces l Maintains a 2-bit counter that specifies the word offset to be loaded into the cache

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 14 Controller State Machine 0 3 Read-hit Read-miss rrdy==1 rdrdy==1 Read-complete && rdrdy==0 5 Write wacpt==1 wacpt==0 && Hit 67 wacpt==1 wacpt==0 rdrdy==1 reset 8 wacpt==0 && Miss always macc =0 || Read-incomplete && rdrdy==0 wacpt==0 wacpt==1 wacpt==0 wacpt==1 rdrdy==0 rrdy==0

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 15 Use Counter to Read Four Words 0 3 Read-hit Read-miss rrdy=1 rdrdy=1 Read-complete 5 Other Write wacpt=1 wacpt=0, hit 67 wacpt=1 wacpt=0 rdrdy=1 reset 8 wacpt=0, miss always macc =0 || Read-incomplete 32 rdrdy= rdrdy=0

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 16 States for Read Miss addressdata0data1data2data3 Read request Read ready Read data ready Read data accept

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 17 States for Write Hit addressdata Write request Write accept

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 18 States for Write Miss Read request addrdata data0data1data2data3 Read data ready Read data accept Write reqst Write acpt data

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 19 ProcInterface Block l Receives blockdata from CacheData block as input l Generates outputs for the LC-3 CPU » Sets dout[15:0] to the currently selected value » Sets complete to 1 on a read hit or on state 8 for other cases

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 20 ProcInterface Schematic

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 21 MemInterface Block l Generates outputs for the off-chip memory » sets rrqst, rdacpt, and wrqst depending on state » sets offdata to addr or din or high-impedance (Z), depending on state » block contains combinational logic only (no registers)

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 22 ValidArray Block l Maintains the register of Valid-Bits for the Cache l Outputs the valid-bit for the current cache-index to the CacheData block (depending on address from the LC-3 CPU) l After all memory-accesses, sets the valid-bit to true for the currently selected cache-index

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 23 ValidArray Schematic l When reset is 1, set all valid bits to 0 l When state is 8, set valid-bit for current index to 1

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 24 Note Top-Level Connections l index[3:0] connects to addr[5:2] in top-level

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 25 CacheData Block l Maintains CacheRAM l Reads and Writes to CacheRAM through Block- Registers l Receives Data Output from Off-Chip Memory l Determines whether or not there has been a Cache- Miss l Provides data for LC-3 CPU to ProcInterface Block

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 26 CacheData Schematic l Internal control signals » ramrd » blocksel0-3 l Asynchronous CacheRAM block » when rd is 1, reads memory » when rd is 0, data is high-impedence, writes memory » CacheRAM is provided for you

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 27 CacheRAM Model module CacheRAM(data, addr, rd); input [3:0] addr; inout [73:0] data; input rd; reg [73:0] memarray[15:0]; assign data=(rd==1)?memarray[addr]:74'hz; or addr or rd) if(rd==0) memarray[addr]=data; endmodule

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 28 CacheData Internal Signals l ramrd – 1 when the CacheRAM is being read, 0 when it is being written. Should be 1 at all times except » when current state is 3 (allows writing the values on a cache miss) » when current state is 5 and there is a cache hit. (allows writing the values on a write hit) l blocksel0-3 – control the values written to the block-registers on each cycle. The current output from the CacheRAM should always be written to the block-registers, except for the following two cases: » In state 4, the block-register indicated by the offset bits (bits [1:0] of the address from the LC-3 CPU) should get din[15:0] from the LC-3 CPU. » In state 2, the block-register indicated by the count from the CacheController should get offdata[15:0] from the off-chip memory. l miss – Should be 1 in either of the following cases » the current valid bit is 0 » the current valid bit is 1 and the tag for the current index does not match addr[15:6]