Project 1

 Two parts Implement a 3 bit Gray Code Counter Implement a 4-to-1 muxtiplexer  Can be done on Altera (Quartis) or Xilinx 8/22/2012 – ECE 3561 Lect 2 Copyright Joanne DeGroat, ECE, OSU2

The Gray Code counter  1-bit Gray Code Simply the sequence  2-bit Gray Code 00Can be generated from the 01 1-bit by reflecting. On the top 11prepend 0 – on the bottom 10prepend 1 8/22/2012 – ECE 3561 Lect 2 Copyright Joanne DeGroat, ECE, OSU3

Can now further extend  3-bit Gray Code (again done by prepending) /22/2012 – ECE 3561 Lect 2 Copyright Joanne DeGroat, ECE, OSU4

The VHDL Code for this  Can be accessed via the course web page -- This is the description of a 3 bit Gray Code counter. ENTITY cnt3 IS PORT (clk : IN bit; cnt : OUT bit_vector(2 downto 0)); END cnt3; ARCHITECTURE one OF cnt3 IS SIGNAL state,next_state : bit_vector(2 downto 0) := "000"; BEGIN 8/22/2012 – ECE 3561 Lect 2 Copyright Joanne DeGroat, ECE, OSU5

VHDL CODE in architecture  Code to latch next_state to state -- Latching logic specification PROCESS BEGIN WAIT UNTIL clk='1' AND clk'event; state <= next_state; END PROCESS; 8/22/2012 – ECE 3561 Lect 2 Copyright Joanne DeGroat, ECE, OSU6

Next State generation  --Next state logic for true logid PROCESS (state) BEGIN CASE state IS WHEN ("000") => next_state <= "001"; WHEN ("001") => next_state <= "011"; WHEN ("011") => next_state <= "010"; WHEN ("010") => next_state <= "110"; WHEN ("110") => next_state <= "111"; WHEN ("111") => next_state <= "101"; WHEN ("101") => next_state <= "100"; WHEN ("100") => next_state <= "000"; END CASE; END PROCESS;  8/22/2012 – ECE 3561 Lect 2 Copyright Joanne DeGroat, ECE, OSU7

Output the state -- Assign outputs cnt <= state; END one;  Here assigning the output is very straightforward. Typically output assignment is simple, especially from a Moore type machine. 8/22/2012 – ECE 3561 Lect 2 Copyright Joanne DeGroat, ECE, OSU8

The 4-to-1 mux  A CMOS implementation 8/22/2012 – ECE 3561 Lect 2 Copyright Joanne DeGroat, ECE, OSU9

HDL code for 4-to-1 mux ENTITY mux4to1 IS PORT (a,b,g0,g1,g2,g3 : IN bit; z : OUT bit); END mux4to1; ARCHITECTURE one OF mux4to1 IS BEGIN z <= (g0 AND NOT a AND NOT b) OR (g1 AND NOT a AND b) OR (g2 AND a AND NOT b) OR (g3 AND a AND b); END one; 8/22/2012 – ECE 3561 Lect 2 Copyright Joanne DeGroat, ECE, OSU10

What to do with HDL code?  Go to the lab or work on your own computer  Enter the HDL into the FGPA software for the counter and the mux – 2 different projects  From the HDL generate the FPGA  Repeat for the 4-to-1 mux only this time do a schematic capture implementation.  Create a report showing The HDL you entered The schematic of the generated circuit Summarize the details of the synthesis – how many LUTs, how many F/Fs, and other details you consider significant. Contrast the results from the HDL and the schematic source for the mux circuit. Submit report to dropbox – PR1 in CARMEN 8/22/2012 – ECE 3561 Lect 2 Copyright Joanne DeGroat, ECE, OSU11

Generated FPGA in XILINX  What the schematic looks like 8/22/2012 – ECE 3561 Lect 2 Copyright Joanne DeGroat, ECE, OSU12

Objective  Have fun and learn  Notes of caution: You will get error messages that don’t really tell you the problem. The project name need to be the same as the entity name of the top level design unit. 8/22/2012 – ECE 3561 Lect 2 Copyright Joanne DeGroat, ECE, OSU13