HW5 and Final Project Yield Estimation and Optimization for 6-T SRAM Cell Fang Gong

Outline Introduction Background HomeWork 5 [due on Feb. 20] Final Project [due on March. 15]

Process Variation Process Variation becomes larger with technology scaling Larger Variations lead to lower Yield Rate Yield Rate is defined as It is significant to estimate and further optimize the yield rate considering process variation!

Impact of Process Variations in SRAM Cell Intra-die process variations  device mismatch in SRAM cell  cell failure In particular: random dopant fluctuation  threshold voltage variations in memory cell Parametric Failures n Read Failure n Write-Failure

SRAM reading failure SRAM 6T Cell considering Reading Failure Initially, BL and BLB are pre-charged to ‘1’ (high voltage). When reading the SRAM cell, the WL becomes ‘1’, and hold for a while. When WL becomes ‘1’, the BLB starts to discharge from high voltage, and produces a voltage difference ΔV between it and BL. The time for BLB to produce a large enough ΔV is t d. If t d is larger than the threshold, this leads to an reading failure. tdtd ΔVΔV

SRAM writing Failure SRAM 6T Cell considering Writing Failure Initially, BL is pre-charged to ‘1’ (high voltage) and BLB is ‘0’. When writing the SRAM cell, the WL becomes ‘1’, and hold for a while. When WL becomes ‘1’, the “data” node starts to increase to high voltage and “ndata” node starts to discharge to low voltage. The time for voltage at “data” node becomes larger than that at “ndata” is t d. If t d is larger than the WL hold time, this leads to an writing failure. tdtd L ndata WL data

Yield Estimation for SRAM Yield Rate Estimation for SRAM Cell considering reading failure The threshold voltage (Vth) and Channel Length (Leff) can be derivate from the nominal value in the design stage due to process variation. The variable parameters (Vth, Leff) can change the discharge speed at BLB, and lead to reading failure. The yield constraint can be given as: At the time-step T max, the voltage difference between BL and BLB should be larger than. ΔV threshold Nominal case Variational case

Outline Introduction Background n Methods in Performance Domain n Methods in Parameter Domain HomeWork 5 [due on Feb. 20] Final Project [due on March. 15]

Yield Estimation Strategy Yield Estimation Techniques can be estimated in two space: n Performance domain: contains all possible performance merits of interest.  obtained from simulations over different parameter samplings. – Monte Carlo method, Quasi Monte Carlo, Importance Sampling, Response Surface Model and etc. n Parameter domain: bounded by min and max of all process parameters with consideration of their correlations. – Nonlinear Surface Sampling, Surface-point Finding Strategy and etc.

Direct Monte Carlo Method Traditional Monte Carlo Method Steps: n Sampling within the entire parameter domain according to the probability distribution. n Perform circuit simulation with each set of sampled parameters to obtain a performance merit value. n Yield can be estimate with percentage of samplings with acceptable performance when compared with the given performance constraints. Variable parameters Monte Carlo method is highly time-consuming! Performance Space

Quasi- Monte Carlo Quasi-Monte Carlo (QMC) uses quasi-random sequences rather than random samplings. QMC steps: n Generate quasi-random numbers following specific distributions. n Convert them to random numbers following desired distribution. n Perform simulations and find the yield rate. For example, Sobol sequence follows a uniform distribution n Can be converted to Gaussian distribution using n is the inverse cumulative distribution function (inverse CDF) of the Gaussian distribution. x follows the Gaussian distribution.

Quasi- Monte Carlo (cont.) QMC vs. MC n QMC uses deterministic quasi-random sequences so that to cover the entire parameter space with fewer samplings. n For example, both method use 200 samplings and lead to different results. n QMC can converge with O(1/N), much faster than MC (O(1/sqrt(N))) Samplings from QMC Samplings from MC

Importance Sampling Method Traditional Monte Carlo method is very time-consuming. Modifying the sampling distribution according to performance distribution When applied properly, enormous samplings (several orders of magnitude) can be avoided.

Sampling Distribution Example Assume the initial parameter distribution is normal distribution, and samples at tail region have large probability to be fail. MC wastes a lot of time to sampling around the mean rather than in the tails. Modified Sampling distribution: n Step 1: Perform MC with uniform distribution to find the failure region; n Step 2: Shift the natural distribution into the failure region Difficulty: n It is usually difficult to obtain the optimal sampling distribution.

IS Example for SRAM Cell Case Sampling from MC in parameter domainSampling from IS in parameter domain

Response Surface Model (RSM) Statistical Device Models: n Define a set of random variables {Δx1, Δx2,...} n BSIM parameters are modeled as function of Δxi’s

Basic Idea in RSM Response Surface Modeling method approximate circuit performance (e.g. delay) as an analytical function of all process variations (e.g.  V TH, etc ) – Hide complicated circuit simulation. – Result in a multi-dimensional model fitting problem. Response Surface Model can be used to – Estimate performance variability – Identify critical variation sources – Handle high dimensionality – Etc.

High Dimensionality Process variation must be modeled by a large number of independent random variables – Results in high-dimensional variation space Example: 65nm CMOS process – About 10 independent random variables to model the random variations of a single transistor Circuit NameTransistor #random Variable # SRAM Cell~ 6~ 60 OpAmp~ 50~ 500 ADC~ 2K~ 20K

Implementation Method Linear modeling example: n Generate sampling points n Solve model coefficients by over-determined linear equations Accuracy can be improved by using 2 or more order function.

CPU Runtime Comparison for SRAM Cell Example Only consider access time failure during reading operation Compare runtime from different methods in performance domain

Outline Introduction Background n Methods in Performance Domain n Methods in Parameter Domain HomeWork 5 [due on Feb. 20] Final Project [due on March. 15]

Yield Surface in Parameter Space Parameter space is the space bounded by the min and max of all parameters around nominal values Yield surface separates success region from failure region n success region  lead to acceptable performance Success region Yield Boundary ƒ m (γ p )=ƒ worst Yield Boundary: 2-D problem Yield Surface: 3-D or higher dimensional problems

Success region Fail region Definition of Yield by Yield Surface n S success : the region where parameters lead to successful performance. n S entire : the entire space that variable parameters can be reached Assume uniform distributions Yield = S success / S entire *Luc Devroye. Non-Uniform Random Variate Generation. New York: Springer-Verlag, 1986.

ƒ m (γ p )=ƒ worst Framework of Nonlinear Surface Sampling (1) Describe circuit by differential algebraic equation (DAE) system → performance surface Performance constraints → constraint plane Yield boundary is the projection of intersection boundary Local searches Reference: P. Cox, P. Yang, and P. Chatterjee, IEDM’83; S. Srivastava and J. Roychowdhury, CICC’07; C. Gu and J. Roychowdhury, ASPDAC2008

Nonlinear Surface Sampling (2) p1p1 p2p2 p0p0 Multiple local searches along tangent direction of DAE for one point on yield surface  1.Perform SPICE simulation with initial parameters; 2.Compare performance merit with performance constraints; 3.If not satisfied, select new parameters and repeat. How to locate the yield boundary in the parameter space with global search?

Surface-point Finding Strategy (QuickYield) Existing MethodQuickYield Including performance constraints in DAE system Introduce variable parameters as unknowns

Surface Point Identification Parameter finding is initially for device optimization, and is applied in yield estimation Original circuit in DAE representation: performance constraint can be integrated into DAE system as: The nonlinear system can be solved with Newton-Raphson Iterations. Yield Boundary

Example: 3 stage Ring Oscillator Consider period as performance merit. Introduce Vth variation to the two MOSFETs in the first stage. QuickYield can provide high accuracy. QuickYield can achieve up to 519X speedup over MC.

Outline Introduction Background HomeWork 5 [due on Feb. 20] Final Project [due on March. 15]

Homework 5 Yield Estimation using Monte Carlo and QMC Methods n Consider “access time failure” : the time that voltage difference between BL_B and BL becomes larger than certain value. n The schematic are shown as below Initial Value: BL_B=1; Q_B=0; Q=1; BL=1; Variation Source: 1.V th (threshold voltage) of Mn1 and Mn2 2.L eff of Mn1 and Mn2 Device Model: Use BSIM3 model for all MOSFETs

netlist Netlist for 6-T cell SRAM * SRAM netlist Vdd dd 0 5 Mn nmos Mn nmos Mn nmos Mn nmos Mp5 3 2 dd dd pmos Mp6 2 3 dd dd pmos all MOSFETs should use BSIM3 model

Detailed Steps Performance Constraint: The voltage difference between BL_B and BL should be larger than ∆v at the time-step t thresh. Use Monte-Carlo and Quasi-Monte Carlo to calculate the yield Y, which is the percentage of circuits with satisfied performance. Steps: – (1) Use MC and QMC to generate random sequences for two variable parameters with Matlab code. – (2) Perform transient simulations with these sequences, and compare the variable performance with constraint. – (3) Calculate the yield rate with definition. Nominal Values, Performance Constraint and required Matlab code will be posted on wiki website

Outline Introduction Background HomeWork 5 Final Project [due on March. 15]

Yield Optimization in Parameter domain Yield Optimization by changing nominal values – Take two variable parameter case as an example each parameter can change within its feasible range determined by process technology. The nominal parameters can lead to successful performance. As the parameters move away from the design point, the circuit's performance also changes away from its nominal value. there exists a region around the nominal design point where the performance remains acceptable It is possible to improve the yield rate by choosing optimal nominal values. rectangular is the box [p1min, p1max]×[p2min, p2max]

Variable Parameter Specification There are four (independent) variable parameters: M1 V th and L eff (Nominal Value: V th = V, L eff = 0.1um) M2 V th and L eff (Nominal Value: V th = V, L eff = 0.1um) They have variations of Gaussian distributions The [min, max] and variation (3σ) for each parameters are: V th : min = 0.2V, max = 0.5V, 3σ=30% of nominal value L eff : min = 0.095um, max = 0.105um, 3σ=10% of nominal value Note: nominal values for other invariable parameters can be found in provided files.

Performance Constraints Performance Constraints should be satisfied at the same time: – (1) Reading and Writing Failure:  Reading: voltage difference between BL and BLB should be larger than (1.3V-109.3mV) at time step 10ps.  Writing: voltage at “data” node should be larger than voltage at “ndata” node at time step 41ps – (2) The Power Consumption at the nominal point should be smaller than initial design. – (3) The Area at the nominal point should be smaller than initial design The optimal design should have largest Yield rate (considering process variations), and minimum power consumption and area. – Yield rate is the most important performance constraint. Efficiency Efficiency is also Important, the CPU Rum-Time should be kept lowest.

Baseline Algorithm (1) The straightforward way is to do exhaust-search in the design space. Step 1: generate sample sequences for all variable parameters with QMC M1-Leff(nm) M1-Vth(V) M2-Leff(nm) M2-Vth(V) Leff (nm)

Baseline Algorithm (2) Step 2: Generate SPICE Net-list file to do MC simulations.

Baseline Algorithm (3) Step 3: Parse the SPICE output to extract the voltage at 10ps, and power consumption. Step 4: Calculate the Yield Rate with performance constraint. Step 5: Select the optimal design point by comparing the Yield Rate, Power and Area.

Baseline Algorithm (4) – Experiment Power (W)Area(m 2 ) Yield (only reading) Yield ( only writing) Yield (reading + writing) Initial Design e e Optimal Design E e Table II. Performance Comparison Mn1 Leff (m)Mn1 Vth (V)Mn2 Leff (m)Mn2 Vth (V) Initial Design1e e Optimal Design9.5e e-80.2 Table I. Nominal Parameter Comparison You may find multiple parameter points for optimal design.

Final Project Description Now, It is your turn to obtain the optimal design by choosing optimal nominal values for variable parameters and considering following constraints at the same time: (1) Yield Rate: With the optimal nominal values, the yield rate should be maximum considering both reading and writing failures. (2) Power Consumption: The optimal design should have smaller Power Consumption than initial design. (3) Area: The optimal design should have smaller Area than initial design. (4) Run-Time: PLEASE use as LESS Monte Carlo simulations as possible. Note: Please report all these performances in your report, and explain why your method can be efficient and accurate.

Thank you!