CEC 220 Digital Circuit Design Introduction to VHDL Wed, Oct 14 CEC 220 Digital Circuit Design Slide 1 of 19

Lecture Outline Wed, Oct 14 CEC 220 Digital Circuit Design Introduction to VHDL  VHDL - (VHSIC) Hardware Description Language o VHSIC - Very High Speed Integrated Circuit Slide 2 of 19

Introduction to VHDL Wed, Oct 14 CEC 220 Digital Circuit Design Large digital systems are unwieldy to design manually  E.g., design a h.264 video transcoder Hardware Description Languages (HDL) allow for design automation  Design  Simulation  Synthesis  Verification RTL: Register Transfer Level ESL: Electronic Sys Level Slide 3 of 19

Introduction to VHDL Wed, Oct 14 CEC 220 Digital Circuit Design History of VHDL  In December 1987, VHDL became IEEE Standard  In September 1993, VHDL was restandardized to clarify and enhance the language (IEEE Standard )  In February 2008 VHDL 2008 (i.e., VHDL 4.0) was approved and IEEE was published in January VHDL is an international standard specification language for describing digital hardware used by industry worldwide VHDL enables hardware modelling from gates to system-level Slide 4 of 19

Introduction to VHDL Wed, Oct 14 CEC 220 Digital Circuit Design VHDL can describe a digital system at  The Behavioral level,  The Structural level, or  The Data-Flow level. Example of a full adder:  Behavioral level: o A functional description: C <= A + B; » A, B, and C may be integers and ‘+’ an arithmetic operator – No implementation details – A high-level description Slide 5 of 19

Introduction to VHDL Wed, Oct 14 CEC 220 Digital Circuit Design  Structural level: o Schematic with gates:  Data-Flow level : o Logic equations: – Sum <= A xor … ; – Cout <= (A and B) or … ; VHDL leads naturally to a top-down design methodology Slide 6 of 19

Introduction to VHDL VHDL Description of Combinational Logic Circuits Wed, Oct 14 CEC 220 Digital Circuit Design Basic example: E <= D or (A and B); Signal_Name <= Expression; Behavioral Description Slide 7 of 19 Assignment operator

Introduction to VHDL VHDL Description of Combinational Logic Circuits Wed, Oct 14 CEC 220 Digital Circuit Design Basic example Assignment operator Concurrent statements Evaluated anytime variables changes If a delay time is not specified then the default is used Dataflow Description Slide 8 of 19

Introduction to VHDL VHDL Description of Combinational Logic Circuits Wed, Oct 14 CEC 220 Digital Circuit Design A Second Example: CLK <= not CLK after 10 ns; A concurrent statement nsec Slide 9 of 19

Introduction to VHDL VHDL Description of Combinational Logic Circuits Wed, Oct 14 CEC 220 Digital Circuit Design Consequences of a concurrent statement Slide 10 of 19

Introduction to VHDL VHDL Description of Combinational Logic Circuits Wed, Oct 14 CEC 220 Digital Circuit Design VHDL Syntax:  Signal names and other VHDL identifiers may contain letters, numbers, and the underscore character (_).  An identifier must start with a letter, and it cannot end with an underscore. VHDL is mostly case insensitive.  Thus, C123 and ab_23 are legal identifiers, but 1ABC and ABC_ are not.  Every VHDL statement must be terminated with a semicolon. White space is ignored.  In VHDL double dash (--) precedes a comment.  Words such as and, or, and after are reserved words with special meanings. Slide 11 of 19

Introduction to VHDL VHDL Description of Combinational Logic Circuits Wed, Oct 14 CEC 220 Digital Circuit Design VHDL Operators:  Binary Logical Operators: and, or, nand, nor, xor, xnor  Relational Operators: =, /=,, >=  Shift Operators: sll, srl, sla, sra, rol, ror  Arithmetic Operators: +, -, &, *, /, mod, rem concatenation Slide 12 of 19

Introduction to VHDL Precedence of VHDL Operators Wed, Oct 14 CEC 220 Digital Circuit Design Slide 13 of 19

Introduction to VHDL Precedence of VHDL Operators Wed, Oct 14 CEC 220 Digital Circuit Design Highest precedence first, then left to right within same precedence group,  Use parenthesis to control order.  Unary operators take an operand on the right. Slide 14 of 19 E <= D or A and B; E <= (D or A) and B; E <= D or (A and B); Which (if any) of these are the same?

Introduction to VHDL VHDL Description of Combinational Logic Circuits Wed, Oct 14 CEC 220 Digital Circuit Design Vector Operations Vector Notation: Slide 15 of 19

Introduction to VHDL VHDL Description of Combinational Logic Circuits Wed, Oct 14 CEC 220 Digital Circuit Design VHDL Models for Multiplexers sel <= A & B; -- select signal with sel select F <= I0 when “00”, I1 when “01”, I2 when “10”, I3 when “11”; F <= I0 when (A = ‘0’) else I1; Conditional assignment Selective assignment Slide 16 of 19

Introduction to VHDL VHDL Description of Combinational Logic Circuits Wed, Oct 14 CEC 220 Digital Circuit Design Examples:  Implement the following VHDL conditional statement using two 2:1 MUXs: o F <= A when D=‘1’ else (B when E = ‘1’ else C);  Given that A <= “01101” and B <= “11100”, what is the value of: o F<= (not B & ‘1’ or A & ‘1’) and ‘1’ & A; ( or ) and (011111) and Slide 17 of 19 F D A E B C

Introduction to VHDL VHDL Description of Combinational Logic Circuits Wed, Oct 14 CEC 220 Digital Circuit Design F <= X nand Y after 4 ns; X <= A nand B after 4 ns; Y <= C nand D after 4 ns; Slide 18 of 19

Next Lecture Wed, Oct 14 CEC 220 Digital Circuit Design More VHDL  Entity, architecture, modules, arrays, … Slide 19 of 19