Standard electronics for CLIC module. Sébastien Vilalte CTC

CTC Sébastien VILALTE General specifications of a crate Problems met end 2009 in CTF3 refocused the developments on several points that are essential for the reliability of a large acquisition system : Radiation hardness: all parts need special care but above all digital parts. Network: even rad-hard, the architecture has to be well suited to long sections of accelerators with rare access. → Compromises between serial/parallel architectures for reliability-simplicity. → Choices depend on future needs: synchronization with the machine, rate… Simplification of the system: minimum number of components, digitalization as soon as possible. → allows a standardization by the use of mezzanines for front sub-systems. Simplification of the analog BPM read-out chain.

CTC Sébastien VILALTE General specifications of a crate Starting specifications for a crate: Discussions with Lars Soby converged to the choice of a standard crate per module: → about 100 signals to acquire every 2m. Industrial standard mechanical crate with local power supplies and network distributed on the back –plane. Generic instrumentation boards. 1 service board: autonomous 12VDC power supplies performed from 230VAC line, network distribution, calibration generator(?)… Several standard instrumentation boards with a simple architecture based on FPGA and mezzanines: different mezzanines developed for the different subsystems with a standard interface (FPGA high speed connectors).

CTC Sébastien VILALTE Crate & architecture Network: The network has to guarantee a synchronous distribution of the machine clock, a data transmission on long distances, radiation hardness, a simple protocol for flexibility, an high speed rate for end concentrated data… The solution is a fiber optic network with a controlled frequency: GBT →high speed network developed by CERN microelectronics department. features: → 4.8Gb/s optical link. → up to 40 local chip-to-chip links, ser-des (data concentration). → Radhard design (xxMrad). → multiple synchronous clocks management. → final version will include slow control features (ADCs, DACs, JTAG, I2C, alarm monitoring…). → future LHC front-end standard network.

CTC Sébastien VILALTE Crate & architecture Each part of the GBT already tested (transceiver, network, laser driver…). Not yet in a final package (2011) but already FPGA interface code available for emulation. Very good contact with CERN microelectronics team and very open collaboration (samples, code...). Also to be defined in the future with the collaboration: Mechanical crate standard: µTCA, ATCA… and back-plane. Network protocol. Number of mezzanines/motherboard and size (also depends on FPGA). More generally, network architecture: Data concentration/distribution boards (switch)? Number of broadcasting tree levels? Final collection of a section: computer? stand-alone system?

CTC Sébastien VILALTE Crate & architecture Standard instrumentation board: Should include a digital part for management of inputs & outputs, management of the local application and power supplies. The digital part can be performed using a single FPGA: → interface with the GBT link via a backplane. → interface with mezzanines dedicated to the different applications. → implementation of a dedicated code for sub-systems applications: signal processing, feedback controls (attenuators, calibrations…). Use of specialized connectors for mezzanines-motherboards links: FMC, HSMC… → allows board upgrades, future local applications developments…

CTC Sébastien VILALTE Crate & architecture Main issue: Radiations. Total dose 15kGy=1,5Mrad for 15 years (simulations) + neutron fluence Radiation on FPGA: Specific FPGA Rad-hard technologies are not adapted for this application (number of cells) and will not be probably supported in the future. Different techniques and technologies allow to limit radiation effects on industrial FPGAs: → small technologies are more resistant to TID and leakage currents anneal total dose effects. TID should be no more a problem for technos<90nm. SEL are limited by the size of the pnpn structure. → code techniques as triple voting fix the problems of non-destructive SEU. → a final hardcopy version could improve the problems due to RAM susceptibility to neutron fluence. → shielding to be studied. Radiation on analog parts and ADCs: not really qualified but selected by experience and known to be much more resistant. Rad-hard DC-DC converters developed by CERN microelectronics group (available 2011). All parts need to be test in radiation environment.

CTC Sébastien VILALTE Crate & architecture BPM acquisition mezzanines: Read-out chain simplified according to specifications: removal of analog preamplifier module. → Power consumption reduced. → simple low noise analog chain with two ranges (or more). → use of quad ADCs for CMRR: 14bits, up to 125Msps (LTC2175). → clock management for low jitter acquisition and synchronization on machine clock. Service board: Local 12VDC power supplies provided from 230VAC line rectification. → crate power consumption to define; 100W seems to be a maximum not to exeed (max.150W available). About 10W per instrumentation board estimated. Should host GBT network.

Evaluation board GBT is not yet available in a final version but can be emulated using FPGA code developed by GBT collaboration. Before crate prototyping, a development of an evaluation board to test architectures, GBT and mezzanine boards is essential: Test of the GBT optical link and protocol. Test of several GBT local back-plane links in parallel (e-link), emulation of several instrumentation boards: synchronization, clocks, rates… Possibility in the future to implement the final GBT transceiver on the board and so to test it. Test of mezzanine subsystems boards. In the BPM acquisition case, implementation of two ADCs on each mezzanine to test synchronization, dynamic ranges, CMRR… Future development and tests of mezzanines for other applications. Tests of high frequency connectors for mezzanines. Possibility to deport mezzanines for radiation qualifications on components (up to 3-4m). Test of power supplies solutions. CTC Sébastien VILALTE

Evaluation board CTC Sébastien VILALTE ARIA II FPGA e-port ARIA II FPGA e-port Clk Mezzanine 1 ADC X 2 Mezzanine 2 STRATIX IV FPGA « GBT » e-port transcievers Clk Optical line X4 Power supplies HSMC MOTHERBOARD

Milestones, prospects Evaluation board: components are chosen, architecture is fixed, currently PCB design. first results for fall Advantage: versatility, will be able to test future ideas. Crate: specifications will fix the final board architecture. Results on evaluation board will allow to design a first prototype: In the future, ADCs sampling rates and dynamics will increase. Mezzanines architecture will allow to upgrade systems. Because of machine rate, FPGA speed will not be the limitation. LAPP funding: manpower 3FTE, 30k€. CTC Sébastien VILALTE