13Apr05 Directors Review Apr ’05 Status of the AFEII(-t) AFEII proto testing AFEII (-t or final) design Paul Rubinov and Stefano Rapisarda

13Apr05 PMR 2 Outline 1.Status of the AFEII prototypes testing 2.AFEII design 3.Changes from AFEII prototypes to AFEII production

13Apr05 PMR 3 Status of the AFEII(-t)  AFEII proto is a huge change from AFEI u Design by John Anderson/layout J Chramowicz u Used existing TriP chips u Changed only what had to be changed (a lot!) remove 8 SVX/32 SIFT/8 CPLD/PIC14000 add 8 FPGA/16 TriP/16 ADCs/LDOs/Flash/PIC16F

13Apr05 PMR 4 AFEII prototype  Key point of the AFEII is to fix the issues with AFEI by ARCHITECTURE  This WORKED. Juan’s talk shows that- the TriP/ADC/FPGA works on the AFEII prototypes.  AFEII prototype is not perfect. Many new* things worked well. Some did not.  AFEII design must change to fix what needs fixing without breaking what works. *new here means not on AFEI

13Apr05 PMR 5 Status of the AFEII(-t)  AFEII proto to AFEII final is a smaller step, but still need to make changes u Things we learned from the AFEII proto u Changes to accommodate TriP-t u Changes to accommodate what has recently been learned about getting the 53 Mhz readout to work

13Apr05 PMR 6 AFEII testing  We received 3 boards in Nov ’04  There was a lot of small stuff that had to be addressed- part values, left/right differences, etc.  Initial boards came up ok, up to a point, then hit a snag* u Worked around it but also worked on it *programming all 8 FPGA from the flash

13Apr05 PMR 7 AFEII testing  Balance of proto boards, 18 u Delivered March 8  The following 3 slides are from the testing plan I presented Feb 18 th u The point is we are following our plan and you can see where we are (Testing team: Kwame Bowie, Zonghan Shi, Neal Wilcer, Joshua Moua)

13Apr05 PMR 8 AFEII testing plan  Visual inspection u Check board u Check/apply FCOs u Start Checklist Traveler  1 st power up u Check resistance between planes u Check current draw

13Apr05 PMR 9 AFEII testing plan  Firmware loading (we have 3 different kinds of chips on these boards!) u 1553 FPGA/PROM (and check JTAG chain) u Helper CPLD (and all other CPLDs JTAG chain) u PIC microcontroller  Functional testing u 1553 tests u Flash read/write u FPGA power u FPGA programming

13Apr05 PMR 10 AFEII testing plan  Functional testing (cont) u ADCs and DACs u FPGA functions: s Communication Interface s TriP power/communications s TriP operation (charge inject) u LVDS testing u “SVX” readout

13Apr05 PMR 11 AFEII testing  Tests that have been done so far cover  EVERY board except the three (1 st article) sacrificial lambs at DAB3 and FCC  EVERY CHIP ON THE BOARD except: u VSVX (part of 53 Mhz readout)* u LVDS MUX CPLDs (part of LVDS readout) *recent studies of AFEI sequencer readout have shown there is a cross talk problem in the sequencer cable. We need to move the assignment of DVALID pin on the cable to address this issue.

13Apr05 PMR 12 AFEII Testing results  All boards required some additional work after delivery u We knew this- small jobs, some deliberate, some communication/documentation problems that have since been addressed.  All boards went through a very thorough visual inspection u All boards were the same except for a very small number of issues (2) u Quality was in general very good (above what we are used to for something of this size/complexity)

13Apr05 PMR 13 AFEII Testing results  3 boards sailed through testing  Of the 15 remaining boards: u 1 board TriP not testable- our mistake (1) Ok otherwise. u 1 bad TriP, 2 possible bad TriP on 2 boards. (2) s using untested TriP chips this build u 3 possible bad FPGA on 2 boards (2) u problems on 4 boards- 3 were fixed (4) u 1 problem unclear (1) u 3 boards waiting retest (3) u 2 shorts fixed (2)

13Apr05 PMR 14 AFEII Testing results ERROR Summary  3 boards sailed through testing  3 boards fixed for known (now!) problem (component out of tolerance)  1 we made mistake- otherwise ok  3 solder shorts (all in the area of hand rework)  1 stuffing error  1 bad TriP, 2 probable

13Apr05 PMR 15 AFEII Testing conclusion  The point of AFEII prototype testing 1.To understand how long it takes us to test boards: extrapolate from 20 to 280: can we do it in 8 weeks? A: We think this testing validates the plan, since we made it on schedule. IF THE BOARDS BASICALLY WORK we can test 280 in 8 weeks. We can not fix a large number in 8 weeks. 2.Find some working boards!

13Apr05 PMR 16 AFEII Testing conclusion  What we learned  We need a large fraction of the production build to work with little or no debugging/rework. (~50%)  We CAN fix some boards during the 8 weeks of testing- some problems are easy to find and fix (bad parts/ stuffing errors)

13Apr05 PMR 17 AFEII design  Main specs of the AFEII: u to exploit the full potential of TriP-t u to operate without modification to existing power infrastructure u to have same performance for VLPC bias & temp control as AFEI (but be easier to calibrate) u to readout at 53Mhz to sequencers u to provide trigger data within allowed latency time

13Apr05 PMR 18 AFEII design

13Apr05 PMR 19 AFEII design iteration  Functional units u MCM = 2TriP + 2ADC + FPGA + support circuits u VLPC Bias and Temp control u Clockgen generates all the proper clocks for the FPGAs u PIC uP and HELPER and Flash to communicate to all the TriP, program all FPGA u VSVX and Sequencer interface for L3 readout u LVDS interface for trigger readout u 1553 interface for slow control and monitoring u Power

13Apr05 PMR 20 AFEII design iteration u MCM = 2TriP + 2ADC + FPGA + support circuits s This is the heart of the board. s 1 st there were some routing issues between the MCM and PIC/Helper discovered and these need to be fixed. s 2 nd changes are to do a better job of accommodating 53 Mhz readout. s 3 rd changes are to reduce power consumption and dove-tail with changes in the LVDS system.

13Apr05 PMR 21 AFEII design iteration u Bias and Temp control s Significant changes were made here from the AFEI and seem to have worked perfectly. s Circuitry is precise enough but could be more accurate. Need to review the error budgets, but barring any Eureka moments, plan is to include a very simple self calibration capability. (3 precision resistors)

13Apr05 PMR 22 AFEII design iteration u Clockgen s We are evaluating a new part from Lattice has become available that will make this much slicker. John A endorses making this change. This change will reduce part count.

13Apr05 PMR 23 AFEII design iteration u PIC uP and HELPER s “Green wires” from AFEII proto need to be incorporated into the AFEII final board layout. s There is also a layout issue in this area (same as mentioned in the “MCM” slide)

13Apr05 PMR 24 AFEII design iteration u VSVX and Sequencer interface s The VSVX needs to be changed to: s 1 st incorporate what has been learned about 53Mhz readout recently s 2 nd to take better advantage of the difference between SVX chips (on AFEI) and Xilinx FPGAs (on AFEII). (get rid of the 20 inch, high speed, high load bus!)

13Apr05 PMR 25 AFEII design iteration u LVDS interface s Changes here are really changes in the MCM, not the interface itself, but the are related to the LVDS system and are clearer under this heading. This change is architectural s CPLD in every slice is replaced by a small FPGA s 1 st this allows a much more flexible implementation of the LVDS_MUX function. The importance of this increases because of the switch to singlet track finding in the upgraded DFEs. It also helps operational issues. s 2 nd it makes the AFEII more homogeneous and reduces power consumption.

13Apr05 PMR 26 AFEII design iteration u 1553 interface s The analog part of this circuit, which was inherited from our ancient ancestors is proving to be disappointingly sensitive to part variations we are getting. However, it seems the easiest way to deal with this is to check the parts before stuffing (this is very easy). So no (further) changes are being implemented, except for one small addition for diagnostics.

13Apr05 PMR 27 AFEII design iteration u Power s The power dissipation of the AFEII is quite similar to the power dissipation of the AFEI, but the detailed characteristics of the AFEII power are radically different. This is due to the volatile nature of the FPGA vs. static nature of the CPLDs. s The power distribution system on the AFEII prototypes is a success. The plan is to slightly rearrange which chips get power from which voltage tap, to better match the distribution of power available, but no other changes. I judge the risk of introducing noise by use of DC-DC converters too high at this point.

13Apr05 PMR 28 AFEII design conclusion  The critical thing for the success of this project is SCHEDULE  The critical thing for the success of the schedule is a WORKING DESIGN which requires little debugging/fixing

13Apr05 PMR 29 AFEII design conclusion  The plan for getting this done is: u Implement known fixes on schematic (now) u Consider proposed changes (by early May) u Finish implementing reasonable changes (by late May)