FPIX2: A rad-hard pixel readout chip for BTeV David Christian Fermilab Homestead September 14, 2000 Vertex 2000 f

David Christianp2 Vertex 2000 New Fermilab collider experiment (approved in June, 2000) Will be installed in a new interaction region at C0 startup ~ Primary goals: study of CP violation, mixing & rare decays in b and c systems “Two arm” forward spectrometer: central dipole with pixel planes in vacuum – as close to the beam as radiation damage will allow Level 1 trigger based on tracks & vertices reconstructed using pixel data

Pixel readout chip for BTeV: requirements David Christianp3 Vertex 2000 Radiation hard Optimized for 132 ns crossing time Able to tolerate large sensor leakage current High speed zero-suppressed readout We expect the chip we develop for BTeV to be suitable for use by CDF and D0 also

FPIX Designers David Christianp4 Vertex 2000 Abderrezak Mekkaoui: Lead engineer (analog design + overall responsibility) Jim Hoff: Digital design

FPIX Roadmap David Christianp5 Vertex 2000 Pixel size = 50  x 400  (matches ATLAS n + on n test sensors) Target rad-hard technology = Honeywell 0.5  CMOS (SOI) (3 metal, 3.3V) (1 metal layer used for shield between sensor & R/O chip) FPIX0 (1997) HP 0.8  CMOS Close to final analog front end R/O pixel includes a peak sensor – digitized off chip Array size = 12 x 64 Bench tests and beam tests FPIX1 (1998) HP 0.5  CMOS Optimized front end 4 comparators per cell (2-bit FADC) New fast R/O architecture, allows both self-triggered and externally-triggered operation Array size = 18 x 160 Bench tests and beam tests Then (Dec, 1998), a change of plans Try to use deep-submicron CMOS All subsequent prototypes should be rad-hard.

FPIX2 Roadmap David Christianp6 Vertex  CMOS (5 metal [6 possible], 2.5V) Design for 2 vendors (“lowest common denominator” design rules): “CERN” – Very favorable contract, but problems with US Gov. restrictions Taiwan Semiconductor Manufacturing Corp (TSMC) – Available through MOSIS PreFPIX2-T (1999) TSMC 0.25  CMOS New analog front end, with new leakage current compensation strategy 8 comparators per cell (3-bit FADC); no EOC logic included Array size = 2 x 160 Bench tests (radiation exposure) PreFPIX2-I (2000) “CERN” 0.25  CMOS Same front end Complete “core” – including new, simplified EOC & R/O (self-triggered only) Array size = 18 x 32 PreFPIX2-T2 (2000) TSMC 0.25  CMOS New programming interface Internal DAC’s – no external currents required; only external voltages are 2.5V & ground. Array size = 18 x 64 FPIX2 (2001) 0.25  CMOS - Final BTeV R/O chip!!??

50 W to grnd Vin Chip boundary Cinj -V(detector bias) p n Pixel detector First stage feedback element in box:“Synthetic Resistor” = transistor which acts as a resistor for small signals and as a constant current source (discharging the feedback capacitor) for large signals (or large leakage current). unit cell boundary * See Blanquart, et al. NIMA 395, p313 (1997) David Christianp7 Vertex 2000 FPIX0/FPIX1 front end*

High gain cell (9,0) I_fb = 7 nA Leakage current ~ 0 Leakage current ~20 nA/pixel Leakage current ~ 100 nA/pixel Leakage current ~20 nA/pixel Leakage current ~ 0; I_fb = 7 nA High gain cell (9,0) I_fb = 0.5 nA FPIX0 Insensitivity to leakage current: High gain cell can be adjusted so that rise time & amplitude with ~20 nA/pixel of leakage current match the rise time & amplitude with no leakage current. FPIX0 feedback & leakage current compensation David Christianp8 Vertex 2000

Test Sensor Inject FPIX1 front end layout David Christianp9 Vertex st transistor Bump bond Pad (feedback cap is underneath) charge injection capacitor cascode feedback and leakage current compensation transistors: NOTE aspect ratio! I ff V dda

Positive charge trapped in the oxide layer effectively biases the transistors. Gate oxide n+ Source (normally connected to gnd) Drain Conductive channel is induced by positive voltage applied to the gate Gate p bulk “Threshold voltage” shifts with exposure to radiation BUT, the effect gets smaller as the oxide gets thinner (with smaller feature size) … by 0.25m the threshold shifts are small enough to be “benign.” Radiation damage to CMOS transistors David Christianp10 Vertex 2000

Trapped charge in the field oxide also causes leakage current in nmos devices by inducing an n-channel in the p-bulk. source drain pmos leakage current does not increase (glass charges +; doesn’t induce a p-channel). David Christianp11 Radiation induced leakage current Vertex 2000

Rad-hard nfet layout (very schematic!) David Christianp12 Vertex 2000 Or, impossible! Large W/L is “easy” Small W/L is hard “gate all around” layout (guard rings to prevent latchup not shown)

Test Sensor Inject FPIX1 front end layout David Christianp13 Vertex st transistor Bump bond Pad (feedback cap is underneath) charge injection capacitor cascode feedback and leakage current compensation transistors: NOTE aspect ratio! I ff V dda

One NMOS feedback transistor biased by a global voltage VFF. VFF generated such as to track (to the 1st order) the preamp DC level shifts due to global changes (process, temperature…) Feedback is current controlled as before. This current can be much higher than in the previous scheme. It is more reliable to work with higher currents. Leakage current compensation assured by a separate scheme (next slide). FPIX2 feedback solution David Christianp14 Vertex 2000

FPIX2 leakage current compensation David Christianp15 Vertex 2000 Compensates one polarity only (n + on n sensor) Differential amplifier in feedback must have VERY low bandwidth!

Vff Test Sensor Inject Vref Vdda 1 st transistor feedback resistor (transistor) cascode leakage current compensation op amp charge Injection capacitor Bump bond Pad (feedback cap is underneath) Capacitors used to limit frequency response of op amp in Leakage current compensation circuit (pre)FPIX2 front end layout David Christianp16 Vertex 2000

Qin=3260e- channel R. 3 different feedback currents. (pre)FPIX2 pulse shapes David Christianp17 Vertex 2000

After the first nA no change in the response is observed ! (pre)FPIX2 leakage current compensation David Christianp18 Vertex 2000

(pre)FPIX2 Irradiation Tests David Christianp19 Vertex 2000 Just starting irradiation tests! 1 st test used 60 Co source at Argonne After ~33 MRad: Circuits are fully functional No degradation in speed (inferred from kill/inject shift register operation) Less than 10% change in analog power dissipation; less after irradiation. (as expected; due to small V T change in PMOS)

(pre)FPIX2: front end response, before and after irradiation David Christianp20 Vertex 2000 No change in settings (bias voltages, feedback current,…) before/after irradiation

=> Practically no change in noise and threshold dispersion. => 200 e- change in the threshold voltage. (pre)FPIX2 Noise and discriminator threshold distributions David Christianp21 Vertex 2000

Next Steps David Christianp22 Vertex 2000 Irradiation of preFPIX2 chips bump bonded to sensors using protons (Indiana University cyclotron – 200 MeV): Total dose effects Single event effects Latchup Single event upset (single bit errors) Tests of preFPIX2-T2 DAC’s VLDS I/O Final Specification of FPIX2 Array size (18 x 160?) Output format serialized, high speed VLDS? point to point? drive signals out of high-radiation environment?