doc.: IEEE / n Submission March 2004 PCCC Turbo Codes for IEEE n B. Bougard; B. Van Poucke; L. Van der Perre {bougardb, vanpouck, Presented by Bert Gyselinckx IMEC/Wireless Research March 2004

doc.: IEEE / n Submission March 2004 Outline Advanced FEC for WLAN Myths about Turbo-Codes Turbo Codes: preferred choice for WLAN

doc.: IEEE / n Submission March 2004 Outline  Advanced FEC for WLAN Myths about Turbo-Codes Turbo Codes: preferred choice for WLAN

doc.: IEEE / n Submission March 2004 Advanced FECs get close to Shannon’s Limit 1 1/ Spectral Efficiency [bit/s/Hz] Eb/No [dB] Add points (Benedetto) Uncoded QPSK Viterbi+RS SCBC PCCC Regular LDPC Irregular LDPC Shannon Limit 1 1/ Spectral Efficiency [bit/s/Hz] Eb/No [dB] Add points (Benedetto) 1 1/ Spectral Efficiency [bit/s/Hz] Eb/No [dB] Add points (Benedetto) Uncoded QPSK Viterbi+RS SCBC PCCC Regular LDPC Shannon Limit

doc.: IEEE / n Submission March 2004 PCCC and LDPC are close competitors Performance

doc.: IEEE / n Submission March 2004 PCCC and LDPC are close competitors LDPCPCCC Encodero(N 2 )o(N) DecoderN*2N c +M*(2*N r -1) ~10 iterations N*(2 v v+2 +7) ~ 3-6 iterations Complexity Turbo: N: block size; v: constraint length LDPC: N: block size; M: code dimension; Nc: #ones per column of H; #ones per row of H > <

doc.: IEEE / n Submission March 2004 Outline Advanced FEC for WLAN  Myths about Turbo-Codes Turbo Codes: preferred choice for WLAN

doc.: IEEE / n Submission March 2004 Myth 1: PCCCs have poor performance with small blocksize

doc.: IEEE / n Submission March 2004 Myth 2: PCCCs require code termination that reduces code rate Double termination Virtual termination

doc.: IEEE / n Submission March 2004 Myth 3: PCCCs are power hungry Look at the average TX+RX DC power with adaptive modulation over a representative set of channel instances -5%

doc.: IEEE / n Submission March 2004 Outline Advanced FEC for WLAN Myths about Turbo-Codes  Turbo Codes: preferred choice for WLAN

doc.: IEEE / n Submission March 2004 PCCC assets PCCC already recognized in several standards Potential for low latency Potential for low power Flexibility –Unconstrained in blocksize (numerous interleaver sizes possible) –Any code rate achievable by puncturing –Code rate ‘compatible’ with CC scheme –Energy-Scalable architecture possible

doc.: IEEE / n Submission March 2004 Parallel PCCC codec prototype Nominal clock frequency (max)160 MHz (170.9 MHz) Nominal throughput (max)75.6 Mb/s (80.7 Mb/s) Number of gates<400 K Total RAM area36 Kbit Decoding Latency5  s Energy consumption<1.45 nJ/bit This holds for UMC.18  m technology. If mapped in.13  m, the architecture achieves easily 100Mbps with still less latency and energy consumption

doc.: IEEE / n Submission March 2004 Flexibility makes integration in n easy Interleaver size Interleaver size leading to an integer number of coded OFDM symbols without bit stuffing Interleaver sizes = {128, 144, 192, 256, 288, 384, 432} Code rate = {1/3, 1/2, 2/3, 3/4} Virtual termination

doc.: IEEE / n Submission March 2004 Energy-scalability improves the data rate versus energy consumption trade-off Total Rx energy per bit vs. net goodput

doc.: IEEE / n Submission March 2004 Backup

doc.: IEEE / n Submission March 2004 LDPC in a nutshell c.H T =0 Tanner graph Parity check matrix

doc.: IEEE / n Submission March 2004 LDPC in a nutshell: decoding Sum-product algorithm

doc.: IEEE / n Submission March 2004 PCCC in a nutshell DDD ILV DDD SISO 1 DILV SISO ILV s c1c1 c2c2

doc.: IEEE / n Submission March 2004 PCCC in a nutshell: decoding BCJR algorithm

doc.: IEEE / n Submission March 2004 Key References [1]S. B. Wicker, S. Kim, Fundamentals of codes, graphs and iterative decoding, Kluwer Academic Publishers, 2003 [2] A. Giulietti, B. Bougard, L. Van der Perre, Turbo Codes, Desirable and Designable, Kluwer Academic Publisher, 2003 [3]R. G. Gallager, Low Density Parity-Check Codes, Cambridge, MA: MIT Press, 1963 [4]G. Berrou, A. Glavieux, P. Thitimajshima, “Near Shannon limit error-correcting coding and decoding: Turbo Codes”, in Proc. Int. Conf. Commun., Geneva, Switzerland, May 1993 pp [5]C. Schurgers et al., "Memory Optimization of MAP Turbo Decoder Algorithms,“, IEEE Transactions on VLSI Systems, Vol.9, No.2, pp , April [6]A. Giulietti et al., "Parallel turbo code interleavers : avoiding collisions in accesses to storage elements", Electronics Letters, Vol. 38 No. 5, Feb [7]Thul, M.J.; Gilbert, F.; Wehn, N, "Concurrent interleaving architectures for high-throughput channel coding”, in Proc. IEEE ICASSP 2003, Vol. 2, pp April 2003 [8]B. Bougard et al., “A Scalable 837nJ/bit 75Mb/s Parallel Concatenated Convolutional (Turbo-) CODEC”, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Vol. 1., pp , San Francisco, CA, Feb [9]D. J. C. Mac Kay, “Good error correcting codes based on very sparse matrices”, IEEE Trans. Inform. Theory, vol. 45, pp , Mar [10]T. Richardson and R. Urbanke, “Efficient encoding of Low-density parity-check codes”, IEEE Trans. Inform. Theory, vol. 47, pp , Feb. 2001