1. CSCE 211: Digital Logic Design Chin-Tser Huang huangct@cse.sc.edu University of South Carolina

2. Chapter 5: Designing Combinational Systems

3. 10/06/20113 Iterative System A system implemented with multiple copies of a smaller circuit Consider 4-bit adder as an example

4. 10/06/20114 Delay in Combinational Logic Circuits When the input to a gate changes, the output of that gate will not change instantaneously Instead, there is a small delay ∆ If the output of one gate is used as the input to another gate, the delays will add The output is stable after the longest delay path

5. 10/06/20115 Delay in Combinational Logic Circuits Hazard (or glitch)

6. 10/06/20116 Example of Delay

7. 10/06/20117 Cascading 4-bit Adders Can cascade multiple 4-bit adders if larger adders are needed

8. 10/06/20118 Binary Decoder A binary decoder is a device that, when activated, selects one of several output lines, based on a coded input signal The input is an n-bit binary number, and there are 2 n output lines Some decoders also have one or more enable inputs Decoders are often used to select one of many devices

9. 10/06/20119 Active High Decoder

10. 10/06/201110 Active Low Decoder

11. 10/06/201111 Decoder with Enable

12. 10/06/201112 74138 Decoder

13. 10/06/201113 74138 Decoder

14. 10/06/201114 Use 4 3-to-8 Decoders to Select from 32 Devices

15. 10/06/201115 Use Decoder to Enable Another Decoder

16. 10/06/201116 Multiplexers A multiplexer is a switch that passes one of its data inputs through to the output, as a function of a set of select inputs Sets of multiplexers are often used to choose among several multibit input numbers

17. 10/06/201117 Two-way Multiplexer out = w if S = 0; out = x if S = 1

18. 10/06/201118 Four-way Multiplexer

19. 10/06/201119

20. 10/06/201120 Three-variable Function Implemented with Multiplexer

21. 10/06/201121 Gate Arrays Also known as programmable logic device (PLD) or field programmable gate array (FPGA) An efficient way of implementing complicated systems Can implement SOP expressions which are sums of some common product terms

22. 10/06/201122 Structure of a Gate Array

23. 10/06/201123 An Example of Gate Array f = a’b’ + abc g = a’b’c’ + ab + bc h = a’b’ + c

24. 10/06/201124 Three Types of Combinational Logic Arrays Programmable Logic Array (PLA) User specifies all of the connections in both the AND array and the OR array Read-Only Memory (ROM) The AND array is fixed – like a decoder consisting of 2 n AND gates for n inputs User specifies the connections in the OR array Programmable Array Logic (PAL) The connections to the OR gates are specified; user determines the AND gate inputs

25. 10/06/201125 Only need a list of minterms for each function. For example, W(A, B, C, D) = ∑m(3, 7, 8, 9, 11, 15) X(A, B, C, D) = ∑m(3, 4, 5, 7, 10, 14, 15) Y(A, B, C, D) = ∑m(1, 5, 7, 11, 15) Design with Read-Only Memories

26. 10/06/201126 Structure of a PAL