1. CDA 4253 FPGA System Design Behavioral modeling of Combinational Circuits Hao Zheng Dept of Comp Sci & Eng USF

2. 2 Reading P. Chu, FPGA Prototyping by VHDL Examples Chapter 3, RT-level combinational circuit Sections 3.1, 3.2, 3.3, 3.6, 3.7.1, 3.7.3.

3. 3 VHDL Modeling Styles Components and interconnects structural VHDL Descriptions dataflow Concurrent statements behavioral Registers State machines Instruction decoders Sequential statements Subset most suitable for synthesis Testbenches

4. 4 Synthesizable VHDL Dataflow VHDL VHDL code synthesizable VHDL code synthesizable Dataflow VHDL

5. 5 Dataflow Modeling using Concurrent Statements concurrent signal assignment (  ) conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate)

6. 6 Modeling Wires and Buses

7. 7 Signals SIGNAL a : STD_LOGIC; SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0); wire a bus b 1 8

8. 8 Merging Wires and Buses SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL c: STD_LOGIC; SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0); d <= a & b & c; 4 5 10 a b c d

9. 9 Splitting buses SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL c: STD_LOGIC; SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0); a <= d(9 downto 6); b <= d(5 downto 1); c <= d(0); 4 5 10 a b c d

10. Combinational Circuit Building Blocks

11. 11 Fixed Shifters & Rotators

12. 12 Fixed Logical Shift Right in VHDL A(3) A(2) A(1) A(0) ‘0’‘0’A(3)A(2)A(1) A C = C 4 4 A C >>1 L SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0);

13. 13 Fixed Arithmetic Shift Right in VHDL A(3) A(2) A(1) A(0) A(3)A(2)A(1) A C = C 4 4 A C >>1 A(3) A SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0);

14. 14 Fixed Rotation in VHDL A(3) A(2) A(1) A(0) A(2)A(1)A(0)A(3) A 4 4 A C <<< 1 C SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0);

15. 15 Logic Gates

16. 16 Basic Gates – AND, OR, NOT

17. 17 Basic Gates – NAND, NOR … …

18. 18 Basic Gates – XOR (b) Graphical symbol(a) Truth table 0 0 1 1 0 1 0 1 0 1 1 0 x 1 x 2 x 1 x 2 fx 1 x 2  = fx 1 x 2  = (c) Sum-of-products implementation fx 1 x 2  = x 1 x 2

19. 19 Basic Gates – XNOR (b) Graphical symbol(a) Truth table 0 0 1 1 0 1 0 1 1 0 0 1 x 1 x 2 x 1 x 2 fx 1 x 2  = fx 1 x 2  = (c) Sum-of-products implementation fx 1 x 2  = x 1 x 2 x 1 x 2 =.

20. 20 Data-flow VHDL Example x y cin s cout

21. 21 Data-flow VHDL: Example (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fulladd IS PORT(x: IN STD_LOGIC ; y: IN STD_LOGIC ; cin: IN STD_LOGIC ; s: OUT STD_LOGIC ; cout: OUT STD_LOGIC ) ; END fulladd ;

22. 22 Data-flow VHDL: Example (2) ARCHITECTURE dataflow OF fulladd IS BEGIN s <= x XOR y XOR cin ; cout <= (x AND y) OR (cin AND x) OR (cin AND y) ; END dataflow ;

23. 23 Logic Operators Logic operators Logic operators precedence and or nand nor xor not xnor not and or nand nor xor xnor Highest Lowest

24. 24 Wanted: y = ab + cd Incorrect y <= a and b or c and d ; equivalent to y <= ((a and b) or c) and d ; equivalent to y = (ab + c)d Correct y <= (a and b) or (c and d) ; No Implied Precedence

25. 25 Dataflow Model of Multiplexers with Conditional Concurrent Signal Assignment (when-else)

26. 26 2-to-1 Multiplexer (a) Graphical symbol (b) Truth table 0 1 f sel w 0 w 1 f w 0 w 1 0 1

27. 27 VHDL Code for a 2-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT (w0, w1, sel : INSTD_LOGIC ; f : OUTSTD_LOGIC ) ; END mux2to1 ; ARCHITECTURE dataflow OF mux2to1 IS BEGIN f <=w0 WHEN sel = '0' ELSE w1; END dataflow ;

28. 28 Cascade of Multiplexers s1 w 3 w 1 0 1 s2 w 2 0 1 y Notice the priority of selection.

29. 29 Cascade of Multiplexers LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux_cascade IS PORT (w1, w2, w3: IN STD_LOGIC ; s1, s2 : IN STD_LOGIC ; f : OUTSTD_LOGIC ) ; END mux_cascade ; ARCHITECTURE dataflow OF mux_cascade IS BEGIN f <=w1 WHEN s1 =‘1' ELSE w2 WHEN s2 =‘1’ELSE w3; END dataflow ;

30. 30 target_signal <= value1 when condition1 else value2 when condition2 else... value N+1 when condition N+1 else value N ; Conditional Concurrent Signal Assignment

31. 31.… Value N Value N-1 Condition N-1 Condition 2 Condition 1 Value 2 Value 1 Target Signal … 0101 0101 0101 target_signal <= value1 when condition1 else value2 when condition2 else... value N+1 when condition N+1 else value N ; Conditional Concurrent Signal Assignment

32. 32 Relational operators Logic and relational operators precedence More Operators = /= >= not = /= >= and or nand nor xor xnor Highest Lowest

33. 33 compare a = bc Incorrect … when a = b and c else … equivalent to … when (a = b) and c else … Correct … when a = (b and c) else … Precedence of Logic and Relational Operators

34. 34 Dataflow Model of Multiplexers with Selected Concurrent Signal Assignment (with-select-when)

35. 35 f s 1 w 0 w 1 00 01 (b) Truth table w 0 w 1 s 0 w 2 w 3 10 11 0 0 1 1 1 0 1 fs 1 0 s 0 w 2 w 3 (a) Graphic symbol 4-to-1 Multiplexer No priority, and choices are disjoint.

36. 36 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux4to1 IS PORT (w0, w1, w2, w3: IN STD_LOGIC ; s: IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f: OUT STD_LOGIC ) ; END mux4to1 ; ARCHITECTURE dataflow OF mux4to1 IS BEGIN WITH s SELECT f <=w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ; END dataflow; VHDL code for a 4-to-1 Multiplexer

37. 37 Selected Concurrent Signal Assignment with choice_expression select target <= expression1 when choices_1, expression2 when choices_2,... expressionN when choices_N; All choices are mutually exclusive and cover all values of choice_expression.

38. 38 Selected Concurrent Signal Assignment with choice_expression select target <= expression1 when choices_1, expression2 when choices_2,... expressionN when choices_N; choices_1 choices_2 choices_N expression1 target_signal choice expression expression2 expressionN

39. 39 Formats of Choices when Expr when Expr_1 |.... | Expr_N when others

40. 40 Formats of Choices - Example with sel select y <= a when"000", c when"001" | "111", d whenothers;

41. 41 Decoders

42. 42 2-to-4 Decoder 0 0 1 1 1 0 1 y 3 w 1 0 w 0 xx 1 1 0 1 1 En 0 0 1 0 0 y 2 0 1 0 0 0 y 1 1 0 0 0 0 y 0 0 0 0 1 0 w 1 y 3 w 0 y 2 y 1 y 0 (a) Truth table(b) Graphical symbol

43. 43 -- LIBRARY not shown ENTITY dec2to4 IS PORT (w: IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END dec2to4 ; ARCHITECTURE dataflow OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <=“0001" WHEN "100", "0010" WHEN "101", "0100" WHEN "110", “1000" WHEN "111", "0000" WHEN OTHERS ; END dataflow ; VHDL Code for a 2-to-4 Decoder

44. 44 Encoders

45. 45 Priority Encoder w 0 w 3 y 0 y 1 x 0 0 1 0 1 0 w 0 y 1 x y 0 11 0 1 1 1 1 z 1 x x 0 x w 1 0 1 x 0 x w 2 0 0 1 0 x w 3 0 0 0 0 1 z w 1 w 2

46. 46 VHDL code for a Priority Encoder -- library not shown ENTITY priority IS PORT (w: IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; y: OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; z: OUT STD_LOGIC ) ; END priority ; ARCHITECTURE dataflow OF priority IS BEGIN y <="11" when w(3) = '1' else "10" when w(2) = '1' else "01" when w(1) = '1' else "00" ; z <= '0' when w = "0000" else '1' ; END dataflow ;

47. 47 Adders

48. 48 16-bit Unsigned Adder 16 XY CinCout S +

49. 49 Operations on Unsigned Numbers For operations on unsigned numbers USE ieee.numeric_std.all and signals of the type UNSIGNED and conversion functions std_logic_vector(), unsigned() OR USE ieee.std_logic_unsigned.all and signals of the type STD_LOGIC_VECTOR

50. 50 LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all; -- non-IEEE standard ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC ; X : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ; Cout: OUT STD_LOGIC ) ; END adder16 ; ARCHITECTURE dataflow OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ; BEGIN Sum <= ('0' & X) + Y + Cin ; S <= Sum(15 DOWNTO 0) ; Cout <= Sum(16) ; END dataflow ; 16-bit Unsigned Adder

51. 51 Addition of Unsigned Numbers (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.numeric_std.all; -- IEEE standard ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC ; X : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ; Cout: OUT STD_LOGIC ) ; END adder16 ;

52. 52 Addition of Unsigned Numbers (2) ARCHITECTURE dataflow OF adder16 IS SIGNAL Xu:UNSIGNED(15 DOWNTO 0); SIGNAL Yu: UNSIGNED(15 DOWNTO 0); SIGNAL Su : UNSIGNED(16 DOWNTO 0) ; BEGIN Xu <= unsigned(X); Yu <= unsigned(Y); Su <= ('0' & Xu) + Yu + unsigned(‘0’ & Cin) ; S <= std_logic_vector(Su(15 DOWNTO 0)) ; Cout <= Su(16) ; END dataflow ; Signed and unsigned are arrays of std_logic.

53. 53 For operations on signed numbers USE ieee.numeric_std.all, signals of the type SIGNED, and conversion std_logic_vector(), signed() USE ieee.std_logic_signed.all, and signal type STD_LOGIC_VECTOR Operations on Signed Numbers

54. 54 Behave exactly like std_logic_vector They determine whether a given vector should be treated as a signed or unsigned number. Prefer to use ieee.numeric_std.all; Use either numeric_std or std_logic_unsigned(or signed). Do NOT mix them together. Signed/Unsigned Types

55. 55 Multipliers

56. 56 Unsigned vs. Signed Multiplication 1111 x 11100001 15 x 225 1111 x 00000001 x 1 UnsignedSigned In Xilinx, a multiplier can be implemented either in a DSP or CLB

57. 57 8x8-bit Unsigned Multiplier 8 8 ab 16 cU *

58. 58 Multiplication of Unsigned Numbers LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all ; entity multiply is port(a : in STD_LOGIC_VECTOR(7 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); c : out STD_LOGIC_VECTOR(15 downto 0) ); end multiply; architecture dataflow of multiply is begin c <= a * b; end dataflow;

59. 59 8x8-bit Signed Multiplier 8 8 ab 16 cS *

60. 60 Multiplication of Signed Numbers LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all ; entity multiply is port(a : in STD_LOGIC_VECTOR(7 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); c : out STD_LOGIC_VECTOR(15 downto 0) ); end multiply; architecture dataflow of multiply is begin c <= a * b; end dataflow;

61. 61 8x8-bit Unsigned/Signed Multiplier 8 8 ab 16 cu 16 cs *

62. 62 Signed/Unsigned Multiplication library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all ; entity multiply is port(a : in STD_LOGIC_VECTOR(7 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); cu : out STD_LOGIC_VECTOR(15 downto 0); cs : out STD_LOGIC_VECTOR(15 downto 0) ); end multiply; architecture dataflow of multiply is begin -- signed multiplication cs <= std_logic_vector(signed(a)*signed(b)); -- unsigned multiplication cu <= std_logic_vector(unsigned(a)*unsigned(b)); end dataflow;

63. 63 Multiplication with Constants If either A or B in A * B is a constant, more efficient implement with shifts and additions. A * 9 = A << 3 + A

64. 64 Comparators

65. 65 4-bit Number Comparator 4 4 A B AgtB A > B

66. 66 VHDL Code for a 4-bit Unsigned Number Comparator library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_unsigned.all ; entity compare is port(A, B: inSTD_LOGIC_VECTOR(3 downto 0) ; AgtB: outSTD_LOGIC ) ; end compare ; architecture dataflow of compare is begin AgtB B else '0' ; end dataflow ;

67. 67 VHDL Code for a 4-bit Signed Number Comparator library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_signed.all ; entity compare is port(A, B: inSTD_LOGIC_VECTOR(3 downto 0) ; AgtB: outSTD_LOGIC ) ; end compare ; architecture dataflow of compare is begin AgtB B else '0' ; end dataflow ;

68. 68 Tri-State Buffers

69. 69 (b) Equivalent circuit (c) Truth table x f e (a) A tri-state buffer 0 0 1 1 0 1 0 1 Z Z 0 1 f ex x f e = 0 e = 1 x f Tri-State Buffers

70. 70 Four types of Tri-state Buffers

71. 71 Tri-state Buffer – Example (1) LIBRARY ieee; USE ieee.std_logic_1164.all; entity tri_state is port( ena, input:IN STD_LOGIC; output: OUT STD_LOGIC); end tri_state; architecture dataflow of tri_state is begin output <= input when (ena = ‘1’) else ‘Z’; end dataflow;

72. 72 ROM

73. 73 3 16 Addr C 8x16 ROM Dout ROM 8x16 example (1)

74. 74 ROM 8x16 example (2) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; entity rom is port ( Addr : inSTD_LOGIC_VECTOR(2 downto 0); Dout : outSTD_LOGIC_VECTOR(15 downto 0) ); end rom;

75. 75 architecture dataflow of rom is signal temp: integer range 0 to 7; type vector_array is array(0 to 7) of std_logic_vector(15 downto 0); constant memory : vector_array := (X”800A", X"D459", X"A870", X"7853", X"650D", X"642F", X"F742", X"F548"); begin temp<= to_integer(unsigned(Addr)); Dout<= memory(temp); end dataflow; ROM 8x16 example (3)

76. 76 Hexadecimal to 7-Segment Display

77. 77 7-Segment Display A F E D C B G dp To illuminate a segment, the corresponding control signal should be driven low.

78. 78 7-Segment Display A F E D C B G dp To illuminate a segment, the corresponding control signal should be driven low.

79. 79 7-Segment Display A F E D C B G dp To illuminate a segment, the corresponding control signal should be driven low.

80. 80 7-Segment Display All four displays share common segment control signals. Only one display can be illuminated at a time when signal ANx is driven high. A B C D E F G DP

81. 81 7-Segment Display Controller disp_mux 8 8 8 8 in0 in2 in3 sseg an 8 4 hex2sseg 4 4 4 4 clk

82. 82 Binary to BCD Conversion

83. 83 Shift and Add-3 (Double-Dabble) 1.Shift the binary number left one bit. 2.If 8 shifts have taken place, the BCD number is in the Hundreds, Tens, and Units column. 3.If the binary value in any of the BCD columns is 5 or greater, add 3 to that value in that BCD column. 4.Go to 1. Example:

84. 84 Shift and Add-3 (Double-Dabble) 1.Shift the binary number left one bit. 2.If 8 shifts have taken place, the BCD number is in the Hundreds, Tens, and Units column. 3.If the binary value in any of the BCD columns is 5 or greater, add 3 to that value in that BCD column. 4.Go to 1. Example: HundredsTensOnesBinary 0000 11110011

85. 85 Shift and Add-3 (Double-Dabble) HundredsTensOnesBinary Initial000011110011 Shift000111100110 Shift001111001100 Shift011110011000 Add-3101010011000 Shift0001010100110000 Add-30001100000110000 Shift0011000001100000 Shift0110000011000000 Add-31001000011000000 Shift00010010000110000000 Shift00100100001100000000 Goto wiki for more information and VHDL implementation

86. 86 Backup

87. 87 8-bit Variable Rotator Left 8 8 3 A B C A <<< B