1. EE 597G/CSE 578A Project Proposal Presentation Phase-Locked Loop Han-Wei Chen & Ming-Wei Liu The Pennsylvania State University

2. Outline Introduction Architecture & Elements Application Specification Timeline

3. Introduction Phase Lock Loop: PLL is a closed-loop feedback control system that maintains the phase of a signal is a fixed relationship to a reference signal.

4. Introduction Major source of power dissipation are the VCO and frequency divider. A frequency-locked loop synthesizer may not require a frequency divider. 1/R PDF VCO 1/N Loop Filter 10MHz 1/10 900MHz 1/900 Integrator

5. Outline Introduction Architecture & Elements Phase and Frequency Detector and charge Pump Loop Filter VCO

6. PFD with charge pump Compare the phase and Frequency of reference signal and oscillator. Output a current that has an average DC value proportional to the phase error. R2 C2 C1 PFD & Current Charge Pump R V

7. Phase and Frequency Detector

8. Loop Filter 1st-order Steady-State phase error [Zie] 2nd-order or higher Avoid SS phase error Reduce the spur levels [Des b]

9. Voltage-Control Oscillator Using Ring OSC to implement: Odd number of inverters Frequency is controlled by changing the bias of the buffers and hence control the delay. [stanford]

10. Reference [Zie] Principles of Communication: Systems, Modulation and Noise, Wiley; 5 edition (July 27, 2001), R.E. Ziemer [Des b] PLL Performance, Simulation, and Design. 2001. [stanford] http://www-smirc.stanford.edu /

11. Outline Introduction Architecture & Elements Application Specification Timeline

12. Application Since PLL is used for synchronization, its application domain largely resides in various communication domain They are used for: Clock generation Clock recovery Deskewing Spread Spectrum

13. Application Ex: A network router that transmit data over a certain range, a PLL is good at maintaining a constant phase angle relative to a reference signal (i.e. clock synchronization between the host and the client).

14. Application This is especially useful when the data and clock are sent together over a common cable (such as in Manchester coding)

15. Application Other applications like: Deskewing (on the receiver side) If the clock is sent parallel with data Clock generation Precise clock phase even at high frequency Ability of fast switching among different frequencies (Settling Time) can impact system’s response time Demodulation FM Radio, Modem

16. Outline Introduction Architecture & Elements Application Specification Timeline

17. Specification As a reference, we took a snapshot of the LM565, a PLL-IC by National Semiconductors

18. Specification Specification (subject to change)

19. Outline Introduction Architecture & Elements Application Specification Timeline

20. WeekScheduleActualRemarks (1) 2/5-2/11 Initial, Bkgnd Study In ProgressProposal Due (2) 2/12-2/18 PFD (Phase Freq. Detector) (3) 2/19-2/25 PFD / Charge Pump (4) 2/26-3/4 Charge PumpLots of Midterms (5) 3/5-3/11 Loop FilterSpring Break (6) 3/12-3/18 Loop Filter / Freq. Divider Progress Due (7) 3/19-3/25 VCO (V Contd. Oscillators) (8) 3/26-4/1 VCO (9) 4/2-4/8 Bug Fix / Report (10) 4/9-4/15 FinalizeFinal Due Timetable

21. Thank You! Any question or comment? ;-)