Presentation is loading. Please wait.

Presentation is loading. Please wait.

Side ViewTop View Beginning from a silicon wafer.

Published byStuart Harrison Modified over 8 years ago

Similar presentations

Presentation on theme: "Side ViewTop View Beginning from a silicon wafer."— Presentation transcript:

1 Side ViewTop View Beginning from a silicon wafer

2 Side ViewTop View Thermal Oxidation

3 Side ViewTop View Spin-on Photo Resist (PR)

4 Side ViewTop View Alignment, UV Expose and Develop Photo Resist (PR)

5 Side ViewTop View Oxide Etched

6 Side ViewTop View Remove Photo Resist (PR)

7 Side ViewTop View Doping (implantation or diffusion)

8 Side ViewTop View Grow Field Oxide (wet/dry) and dopant diffusion

9 Side ViewTop View Spin-on Photo Resist (PR)

10 Side ViewTop View Alignment, UV Expose and Develop Photo Resist (PR)

11 Side ViewTop View Oxide Etched

12 Side ViewTop View Remove Photo Resist (PR)

13 Side ViewTop View Grow Gate Oxide (dry)

14 Side ViewTop View Spin-on Photo Resist (PR)

15 Side ViewTop View Alignment, UV Expose and Develop Photo Resist (PR)

16 Side ViewTop View Field Oxide Etched

17 Side ViewTop View Field Oxide Etched

18 Side ViewTop View Metal (e.g., Aluminum) deposition

19 Side ViewTop View Spin-on Photo Resist (PR)

20 Side ViewTop View Alignment, UV Expose and Develop Photo Resist (PR)

21 Side ViewTop View Aluminum Etched

22 Side ViewTop View Remove Photo Resist (PR), annealing - complete

Download ppt "Side ViewTop View Beginning from a silicon wafer."

Similar presentations

FABRICATION PROCESSES

FABRICATION PROCESSES
Course: Analog Circuit Design Time schedule: Tu 11.00-13.00 We14.00-16.00 Th14.00-16.00 Office hours: Tu 16.00-18.00 Exams: Feb. (2), Jun.-Jul. (2), Sep.

Course: Analog Circuit Design Time schedule: Tu We Th Office hours: Tu Exams: Feb. (2), Jun.-Jul. (2), Sep.
CHAPTER 8: THERMAL PROCESS (continued). Diffusion Process The process of materials move from high concentration regions to low concentration regions,

CHAPTER 8: THERMAL PROCESS (continued). Diffusion Process The process of materials move from high concentration regions to low concentration regions,
CMOS Fabrication EMT 251.

CMOS Fabrication EMT 251.
Simplified Example of a LOCOS Fabrication Process

Simplified Example of a LOCOS Fabrication Process
CMOS Process at a Glance

CMOS Process at a Glance
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #6.

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #6.

Fabrication of p-n junction in Si Silicon wafer [1-0-0] Type: N Dopant: P Resistivity: 10-20 Ω-cm Thickness: 505-545 µm.

Fabrication of p-n junction in Si Silicon wafer [1-0-0] Type: N Dopant: P Resistivity: Ω-cm Thickness: µm.
Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.

Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.
Device Fabrication Technology

Device Fabrication Technology
Elettronica D. AA 2000-2001 Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.
1 N/P-Channel MOSFET Fabrication By Assoc. Prof Dr. Uda Hashim School of Microelectronic Enginnering KUKUM FOX N-Well Arsenic Implant LDD As+ S/D Implant.

1 N/P-Channel MOSFET Fabrication By Assoc. Prof Dr. Uda Hashim School of Microelectronic Enginnering KUKUM FOX N-Well Arsenic Implant LDD As+ S/D Implant.
The Physical Structure (NMOS)

The Physical Structure (NMOS)
Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill,

Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill,
Lecture #51 Lecture #5 – VLSI Design Review zPhotolithography zPatterning Silicon zProcess steps used are: yStarts with Si wafer yThermal oxidation yPhotoresist.

Lecture #51 Lecture #5 – VLSI Design Review zPhotolithography zPatterning Silicon zProcess steps used are: yStarts with Si wafer yThermal oxidation yPhotoresist.
Sample Devices for NAIL Thermal Imaging and Nanowire Projects Design and Fabrication Mead Mišić Selim Ünlü.

Sample Devices for NAIL Thermal Imaging and Nanowire Projects Design and Fabrication Mead Mišić Selim Ünlü.
Device Fabrication Example

Device Fabrication Example
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process I Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process I Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.
ECE685 Nanoelectronics – Semiconductor Devices Lecture given by Qiliang Li.

ECE685 Nanoelectronics – Semiconductor Devices Lecture given by Qiliang Li.

Similar presentations

Ads by Google