1. Show who is the BOSS Issues with VHDL Synthesis

2. VHDL Simulator versus Synthetiser VHDL Simulator follows the strict VHDL rules. It does not produce a netlist. It is always RIGHT!!! After synthesis, the netlist (so called post-map) simulation shows the actual circuit behaviour which may be different from the VHDL simulation. Lesson: A synthetizer can get it WRONG!!!

3. How to Tame the Synthesiser Adopt VHDL style that facilitates “transparent” synthesis. Partition Design into “simple” functionality hierarchical blocks. Make use of structural descriptions in terms of hardware related components.

4. Example : Binary comparator entity BinComp is port ( M, N in: bit_vector(1 downto 0); EQ out: bit ); end BinComp; architecture behaviour of BinComp is begin EQ <= ‘0’ when M(1) /= N(1) else ‘0’ when M(0) /= N(0) else ‘1’; end behaviour; architecture boolean of BinComp is signal LB_same, HB_same: bit; begin EQ <= LB_same AND HB_same; LB_same <= N(0) XNOR M(0); HB_same <= N(1) XNOR M(1); end boolean;

5. Structural Description architecture structure of BinComp is -- Declarations component XNORgate is -- components (defined elsewhere) port ( x1, x2 : in bit; y : out bit); end component; component ANDgate is port ( x1, x2 : in bit; y : out bit); end component; signal LB_same, HB_same : bit; -- Internal wires begin -- Circuit description in form of a “Schematic” netlist INST1: component XNORgate port map( x1 => M(1), x2 => N(1), y => HB_same); INST2: component XNORgate port map( x1 => M(0), x2 => N(0), y => LB_same); INST3: component ANDgate port map( x1 => LB_same, x2 => HB_same, y => EQ); end structure;