1. Petrify Massoud Daneshtalab Mohammad Riazati

2. VSTGL Tool:.inputs b a.outputs d c.graph P0 b+ a+ P1 b- b+ c+ c+ P1 c- P0 b- c- a+ b+/1 b+/1 d+ d+ c+/1 c+/1 d- d- a- a- P1.marking { P0 }.end ######################## P: P0 418 190 P: P1 247 399 T: b+ 285 266 T: c+ 285 323 T: c- 399 266 T: b- 399 323 T: a+ 532 266 T: b+/1 532 323 T: d+ 532 380 T: c+/1 532 437 T: d- 399 513 T: a- 285 456 # End of Visual STG Lab file. Visual STG Lab is a graphical STG entry and simulation. Developed in Technical University of Denmark

3. Important Options of Petrify: - cg : Will produce a complex-gate circuit - gc : Will produce a generalized C-element circuit. Boolean equations for the set and reset functions for each non-input signal. - gcm : Will produce a generalized C-element circuit. set and reset functions are implemented using simple AND and OR gates. -tm : Technology mapping onto a gate library.

4. Petrify Tool: # EQN file for model e # Generated by petrify 4.2 (compiled 15-Oct-03 at 3:06 PM) # Outputs between brackets "[out]" indicate a feedback to input "out" # Estimated area = 7.00 INORDER = a b c d; OUTORDER = [c] [d]; [c] = b (c + a') + d; [d] = a b c'; Using Complex Gates: > petrify input_file.g -cg -eqn output_file.eqn.inputs b a.outputs d c.graph P0 b+ a+ P1 b- b+ c+ c+ P1 c- P0 b- c- a+ b+/1 b+/1 d+ d+ c+/1 c+/1 d- d- a- a- P1.marking { P0 }.end

5. Petrify Tool:.inputs b a.outputs d c.graph P0 b+ a+ P1 b- b+ c+ c+ P1 c- P0 b- c- a+ b+/1 b+/1 d+ d+ c+/1 c+/1 d- d- a- a- P1.marking { P0 }.end # EQN file for model e # Generated by petrify 4.2 (compiled 15-Oct-03 at 3:06 PM) # Outputs between brackets "[out]" indicate a feedback to input "out" # Estimated area = 16.00 INORDER = a b c d; OUTORDER = [c] [d]; [0] = a' b + d; [1] = a b c'; [d] = c' ([1] + d) + d [1]; # mappable onto gC [c] = b ([0] + c) + c [0]; # mappable onto gC # Set/reset pins: reset(d) Using Generalized C-Elements: > petrify input_file.g -gc -eqn output_file.eqn

6. Petrify Tool:.inputs b a.outputs d c.graph P0 b+ a+ P1 b- b+ c+ c+ P1 c- P0 b- c- a+ b+/1 b+/1 d+ d+ c+/1 c+/1 d- d- a- a- P1.marking { P0 }.end # EQN file for model e # Generated by petrify 4.2 (compiled 15-Oct-03 at 3:06 PM) # Outputs between brackets "[out]" indicate a feedback to input "out" # Estimated area = 12.00 INORDER = a b c d; OUTORDER = [c] [d]; [0] = a' b c' + d; [d] = a b c'; [c] = b ([0] + c) + c [0]; # mappable onto gC Using Standard C-Elements: ( set & reset Function satisfy the monotonic cover constrain.) > petrify input_file.g -gcm -eqn output_file.eqn

7. SIS : SIS is an interactive tool for synthesis and optimization of both combinational and sequential circuits. A Design is specified as an ASTG(Asynchronous Signal Transition Graph), STG (State Transition Graph), or Logic. SIS is used to create a hazard-free logic implementation,optimization and technology mapping. Placement and Routing & Produce a Symbolic Layout for the circuit --> Octtool

8. EQN & BLIF : EQN & BLIF files ( Generated by Petrify ) contains only information readable by SIS. petrify inputfile.g -gcm - eqn outputfile.eqn petrify inputfile.g -gcm - BLIF outputfile.blif

9. Petrify Tool: # BLIF file file for model ex # Generated by./petrify 4.2 (compiled 15-Oct-03 at 3:06 PM) # Estimated area = 7.00.model ex_net.inputs b a.outputs d c.latch [0] d as NIL 0.latch [1] c as NIL 0.names a b c [0] 110 1.names a d b c [1] --11 1 0-1- 1 -1-- 1.end.initial !b !a !d !c ![0] ![1] # No set/reset pins required. Using Complex Gates (BLIF): > petrify input_file.g -cg -blif output_file.eqn.inputs b a.outputs d c.graph P0 b+ a+ P1 b- b+ c+ c+ P1 c- P0 b- c- a+ b+/1 b+/1 d+ d+ c+/1 c+/1 d- d- a- a- P1.marking { P0 }.end

10. More Options : -log logfile.log -CSC : Check and force Complete State Coding

11. Xming : X-c lient of SSH Server.

12. Xming : X-c lient of SSH Server.

13. Xming : X-c lient of SSH Server.

14. Xming : X-c lient of SSH Server.

15. Q & A