1. Static and Dynamic Memory

2. RAM Random Access Memory
Two main types: Static RAM (SRAM) and Dynamic RAM (DRAM)
Differences lie in how bits are stored
Other types: Flash RAM, SDRAM, Video RAM, FERAM

3. Basic RAM Structure

4. Static RAM (SRAM)
Static RAM is a type of RAM that holds its data without external refresh, for as long as power is supplied to the circuit. 
It must be refreshed many times per second in order to hold its data contents. 
SRAM is manufactured in a way rather similar to how processors are: highly-integrated transistor patterns photo-etched into silicon.

5. Static RAM (SRAM)

6. CMOS SRAM cell

7. Static RAM (SRAM)
Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters.
This storage cell has two stable states which are used to denote 0 and 1.
Two additional access transistors serve to control the access to a storage cell during read and write operations.
A typical SRAM uses six MOSFETs to store each memory bit.

8. Memory cell
Memory cells that use fewer than 6 transistors are possible — but such 3T or 1T cells are DRAM, not SRAM.
Access to the cell is enabled by the word line which controls the two access transistors M5 and M6 which, in turn, control whether the cell should be connected to the bit lines: BL and BL. They are used to transfer data for both read and write operations.

9. SRAM Operation An SRAM cell has three different states it can be in:
Standby where the circuit is idle
Reading when the data has been requested
Writing when updating the contents.

10. Standby
If the word line is not asserted, the access transistors M5 and M6 disconnect the cell from the bit lines.
The two cross coupled inverters formed by M1 – M4 will continue to reinforce each other as long as they are connected to the supply.

11. Read and Write Operation
Read: Drive word line, sense value on bit lines
Write: Drive word line, drive new value (strongly) on bit lines

12. DRAM
Dynamic RAM is a type of RAM that only holds its data if it is continuously accessed by special logic called a refresh circuit.
Many hundreds of times each second, this circuitry reads the contents of each memory cell, whether the memory cell is being used at that time by the computer or not.

13. DRAM

14. Memory cell of the DRAM

15. Operations of DRAM
DRAM is usually arranged in a square array of one capacitor and transistor per data bit storage cell. 
The long horizontal lines connecting each row are known as Word Lines.
Each column of cells is actually composed of two bit lines, each one connected to every other storage cell in the column. 

16. Dynamic RAM (DRAM)
Read: Drive word line, sense value on bit line (destroys saved value)
Write: Drive word line, drive new value on bit line.
Process modifications to enhance capacitor storage capacity.

17. Principle of operations of DRAM Read

18. Principle of operations of DRAM Write

19. The End
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