1. © 2005 Xilinx, Inc. All Rights Reserved This material exempt per Department of Commerce license exception TSU CORE Generator System

2. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 3 After completing this module, you will be able to: Objectives Describe the differences between LogiCORE™ and AllianceCORE™ solutions Identify two benefits of using cores in your designs Create customized cores by using the CORE Generator™ software system GUI Instantiate cores into your schematic or HDL design Run behavioral simulation on a design that contains cores

3. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 4 Outline Introduction Using the CORE Generator System CORE Generator Design Flows Summary

4. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 5 What are Cores? A core is a ready-made function that you can instantiate into your design as a black box Cores can range in complexity – Simple arithmetic operators, such as adders, accumulators, and multipliers – System-level building blocks, such as filters, transforms, and memories – Specialized functions, such as bus interfaces, controllers, and microprocessors Some cores can be customized

5. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 6 Benefits of Using Cores Save design time – Cores are created by expert designers who have in-depth knowledge of Xilinx FPGA architecture – Guaranteed functionality saves time during simulation Increase design performance – Cores that contain mapping and placement information have predictable performance that is constant over device size and utilization – The data sheet for each core provides performance expectations Use timing constraints to achieve maximum performance

6. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 7 Types of Cores LogiCORE™ solutions AllianceCORE™ solutions The CORE Generator  system GUI lists the type of each core

7. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 8 LogiCORE Solutions Typically customizable Fully tested, documented, and supported by Xilinx Many are pre-placed for predictable timing Many are unlicensed and provided for free with Xilinx software – More complex LogiCORE™ solution products are licensed VHDL and Verilog flow support for several EDA tools Schematic flow support for most cores

8. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 9 AllianceCORE Solutions Point-solution cores – Typically not customizable (some HDL versions are customizable) Sold and supported by Xilinx AllianceCORE™ solution partners – Partners can be contacted directly to provide customized cores All cores are optimized for Xilinx; some are pre-placed Typically supplied as an Electronic Design Interchange Format (EDIF) netlist VHDL and Verilog flow support; some schematic support

9. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 10 Sample Functions LogiCORE™ solutions – DSP functions Time skew buffers, Finite Impulse Response (FIR) filters, and correlators – Math functions Accumulators, adders, multipliers, integrators, and square root – Memories Pipelined delay elements, single- and dual-port RAM Synchronous FIFOs – PCI master and slave interfaces, PCI bridge AllianceCORE™ solutions – Peripherals DMA controllers Programmable interrupt controllers UARTs – Communications and networking ATM Reed-Solomon encoders and decoders T1 framers – Standard bus interfaces PCMCIA, USB

10. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 11 Outline Introduction Using the CORE Generator System CORE Generator Design Flows Summary

11. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 12 The CORE Generator System A Graphical User Interface (GUI) allows central access to the cores themselves, as well as: – Data sheets – Customizable parameters (available for some cores) Interfaces with design entry tools – Creates graphical symbols for schematic-based designs – Creates instantiation templates for HDL-based designs Web Links tab provides access to the Xilinx Website and the IP Center – The IP Center contains new cores to download and install You always have access to the latest cores

12. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 13 Invoking the CORE Generator System From the Project Navigator, select Project  New Source Select IP (CoreGen & Architecture Wizard) and enter a filename Click Next and then select the type of core

13. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 14 Core Customize Window Parameters tab allows you to customize the core Data sheet access Web Links tab provides direct access to related Web pages Core Overview tab provides version information and a brief functional description Contact tab provides information about the vendor

14. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 15 CORE Data Sheets Features Functionality Pinout Resource utilization Performance expectations (not shown)

15. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 16 Outline Introduction Using the CORE Generator System CORE Generator Design Flows Summary

16. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 17 Schematic Design Flow Generate a core – Select Edit  Project Options to choose a schematic symbol instead of HDL templates – Creates an EDIF file and schematic symbol Instantiate the symbol onto your schematic – Treated as a black box— no underlying schematic Proceed with normal schematic flow Generate Core SimulateInstantiate.EDN and symbol Implement.xco

17. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 18 HDL Design Flow Compile library for behavioral simulation (one time only) Core generation and integration XilinxCoreLib.EDN compxlib.exe Instantiate Simulate.VHD,.V Implement.VHO,.VEO Generate Core.xco

18. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 19 HDL Design Flow: Compile Simulation Library Before your first behavioral simulation, you must run compxlib.exe to compile the XilinxCoreLib simulation library – Located in the $XILINX\bin\ directory – Supports Mentor Graphics ModelSim and SpeedWave, Cadence NC-Verilog, and Synopsys VCS and Scirocco simulation tools If you download new or updated cores, additional simulation models will be automatically extracted during installation

19. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 20 HDL Design Flow: Core Generation and Integration Generate or purchase a core – Netlist file (EDN, NGO) – Instantiation template files (VHO or VEO) – Behavioral simulation wrapper files (VHD or V) Instantiate the core into your HDL source – Cut and paste from the templates provided in the VEO or VHO file The design is ready for synthesis and implementation Use the wrapper files for behavioral simulation – The ISE™ software automatically uses wrapper files when cores are present in the design – VHDL: Analyze the wrapper file for each core before analyzing the file that instantiates the core

20. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 21 Outline Introduction Using the CORE Generator System CORE Generator Design Flows Summary

21. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 22 Skills Check

22. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 23 Review Questions What is the main difference between LogiCORE™ and AllianceCORE™ solution products? What is the purpose of compxlib.exe ? What is the difference between the VHO/VEO files and the VHD/V files that are created by the CORE Generator™ system?

23. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 24 Answers What is the main difference between LogiCORE™ and AllianceCORE™ solution products? – LogiCORE solution products are sold and supported by Xilinx – AllianceCORE solution products are sold and supported by AllianceCORE solution partners What is the purpose of compxlib.exe ? – compxlib.exe makes it easy to compile the XilinxCoreLib library before your first behavioral simulation What is the difference between the VHO/VEO files and the VHD/V files that are created by the CORE Generator™ system? – VHO/VEO files contain instantiation templates – VHD/V files are wrappers for behavioral simulation that reference the XilinxCoreLib library

24. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 25 Summary A core is a ready-made function that you can insert into your design LogiCORE™ solution products are sold and supported by Xilinx AllianceCORE™ solution products are sold and supported by AllianceCORE solution partners Using cores can save design time and provide increased performance Cores can be used in schematic or HDL design flows

25. © 2005 Xilinx, Inc. All Rights Reserved For Academic Use Only Core Generator 26 Where Can I Learn More? Xilinx IP Center: www.xilinx.com/ipcenter – Software updates – Download new cores as they are released Tech Tips on www.xilinx.com  Support Software manuals: CORE Generator Guide – www.xilinx.com  Documentation  Software Manuals