1. Lecture 6: Instruction Set Architecture Computer Engineering 585 Fall 2001

2. Costs of misalignment Word at addr: 2 0 1 2 3 a2=1 4 5 6 7 Memory Multiplexor 3 addr bits: a3, a2, a1 a3=0 a3=1 a2=0

3. memory port Internal bus/reg file Data Alignment Network

4. Addressing Modes Addr mode Example inst Meaning RegisterAdd R4,R3 R[R4]  R  R  R[R3] Immediate Add R4,#3 R[R4 ]  R[R4]+3 constants. DisplacementAdd R4,100(R1) R[R4]  R  R  R[R1]]  local var. Reg deferred Add R4,(R1) pointer IndexedAdd R3,(R1 + R2) Direct Add R1,(1001) static data Mem indirectAdd R1,@(R3) *p. Autoincrement Add R1,(R2)+. Auto- decrement Add R1,-(R2) Scaled Add R1,100(R2)[R3] index arrays R[R4]  R  R  R[R1]] R[R3]  R  R  R[R1]+R[R2]] R[R1]  R  R  1001] R[R1]  R  R  R  R3]]] R[R1]  R  R  R[R2]] R[R2]  R  R  d Array access R[R2]  R  R  d R[R1]  R  R  R[R2]] R[R1]  R  R   R[R2]+ R[R3]  d]

5. Addressing Modes Design Issues an appropriate choice leads to compact code.e.g. where a small constant is needed, keep it in a memory location and then load it into a register vs the use of immediate addr mode. should choose the sizes of various addr mode fields judiciously. e.g. a 32-bit immediate loses all its advantages! program-mix should be used to dictate these decisions:  addr modes: which addr modes should be supported?  displacement size: how large a displacement should be allowed?  immediate size: how large an immediate value should be allowed? Some are architecture independent (immediate size distribution) while some are architecture/compiler dependent (use of different addressing modes).

6. Addressing Modes Usage Register mode: 50%, Displacement: 8, 16, 32-bits, on a VAX

7. Displacement Distribution MIPS, avg of SPEC92, majority of 14+ bits –ve, 1% above 15 bits

8. Immediates vs Inst. class DLX: constant shifts-ALU, compare-0 included

9. Immediates Distribution Vax: 6% < -ve; 50-70% -- 8bits; 75-80% -- 16bits

10. Addressing Modes Summary 50% Register; 22% Displacement; 17% Immediate; 6.3% Register indirect; 3.6% scaled. Displacement: 12-bits capture 75%; 16- bits capture 99% of displacements. Immediates: 8-bits capture 50%; 16- bits capture 80% of immediate values.

11. Instruction Set Operations Operator typeExamples Arithmetic and logical Int arith & logical operations: add, and, subtract, or Data transfer Loads-stores (move instructions) Control Branch, jump, procedure call and return, traps System Operating system call, virtual memory management instructions Floating point Floating-point operations: add, multiply Decimal Decimal add, decimal multiply, decimal-to-character conversions StringString move, string compare, string search GraphicsPixel operations, compression/decompression operations

12. Instruction Set Operations Which operations should be supported? How should the operations of a given class be encoded, say ALU operations? Again, program-mix should be used to dictate these decisions

13. Instruction-Mix: X86

14. Control Flow Instructions Cond. Branches, jumps, procedure call/return Branch instruction: while C doif C thenfor I=x to y do endwhile endifendfor eval Ceval CI=x Br ¬C, +NBr ¬C, +NBr I==y, +N PC-relative Branches: PC+N