1. CSNSM SPIROC : Silicon PM Readout ASIC Stéphane Callier, Frédéric Dulucq, Julien Fleury, Gisèle Martin-Chassard, Christophe de La Taille, Ludovic Raux IN2P3/OMEGA-LAL Orsay

2. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 2 CALICE : imaging calorimetry After LHC : New imaging calorimetry…at the ILC Improve jets measurement by Particle flow algorithm CALICE : 281 phys., 47 labs, 12 countries. Chairperson : JC Brient http://llr.in2p3.fr/activites/physique/flc/calice.htm TCMT AHCAL beam ECAL 90 cm 120 cm SiW ECAL W/Sci SiPM ECAL Sci SiPM AHCAL RPC DHCAL

3. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 3 CALICE AHCAL testbeam prototype Hadronic calorimeter prototype for the ILC : 1 cubic metre, 38 layers, 2cm steel plates 8000 tiles with SiPMs fabricated by MePHY group Mechanics and front end boards: DESY Front end ASICs: LAL FLC_SiPM ASIC Mephy SiPM Also used with W/Sci SiPM japanese ECAL with MPPCs

4. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 4 The front-end ASICs : the ROC chips SPIROC Analog HCAL (SiPM) 36 ch. 32mm² June 07 HARDROC Digital HCAL (RPC, µmegas or GEMs) 64 ch. 16mm² Sept 06 SKIROC ECAL (Si PIN diode) 36 ch. 20mm² Nov 06 Technological prototypes : full scale modules (~2m) EUDET EU funding (06-09) ECAL, AHCAL, DHCAL B=5T

5. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 5 ILC beam structure Acquisition 1ms (.5%) A/D conv..5ms (.25%) DAQ.5ms (.25%) 1% duty cycle IDLE MODE 99% idle cycle 198ms (99%) time Time between two trains: 200ms (5 Hz) Time between two bunch crossing: 337 ns Train length 2820 bunch X (950 µs) Two orders of magnitude saved on the power consumption

6. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 6 Read out : token ring Acquisition A/D conv.DAQIDLE MODE Chip 0 Chip 1 Acquisition A/D conv.DAQIDLE MODEIDLE Chip 2 Acquisition A/D conv.IDLE MODEIDLE Chip 3 Acquisition A/D conv.IDLE MODEIDLE Chip 4 Acquisition A/D conv.IDLE MODEIDLEDAQ Chip 0Chip 1Chip 2Chip 3Chip 4 5 events3 events 0 event 1 event 0 event Data bus

7. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 7 Second generation chip for SiPM SPIROC : Silicon Photomul. Integrated Readout Chip –36 channels –Charge measurement –Time measurement –Autotrigger on MIP or spe –Sparsified readout compatible with EUDET 2 nd generation DAQ –Chips daisy-chained –Pulsed power -> 25 µW/ch Fabricated in SiGe AMS 0.35 µm –Submitted in june 07 –Chip area : 30 mm2

8. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 8 SPIROC main features Internal input 8-bit DAC (0-5V) for individual SiPM gain adjustment Energy measurement : 14 bits –2 gains (1-10) + 12 bit ADC 1 pe  2000 pe –Variable shaping time from 50ns to 100ns –pe/noise ratio : 11 Auto-trigger on 1/3 pe (50fC) –pe/noise ratio on trigger channel : 24 –Fast shaper : ~10ns –Auto-Trigger on ½ pe Time measurement : –12-bit Bunch Crossing ID –12 bit TDC step~100 ps Analog memory for time and charge measurement : depth = 16 Low consumption : ~25µW per channel (in power pulsing mode) Individually addressable calibration injection capacitance Embedded bandgap for voltage references Embedded 10 bit DAC for trigger threshold and gain selection Multiplexed analog output for physics prototype DAQ 4k internal memory and Daisy chain readout

9. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 9 SPIROC : One channel schematic IN test

10. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 10 SPIROC general block scheme DAQ ASIC Chip ID register 8 bits gain Trigger discri Output Wilkinson ADC Discri output gain Trigger discri Output Wilkinson ADC Discri output..… OR36 EndRamp (Discri ADC Wilkinson) 36 TM (Discri trigger) ValGain (low gain or high Gain) ExtSigmaTM (OR36) Channel 1 Channel 0 ValDimGray 12 bits … Acquisition readout Conversion ADC + Ecriture RAM RAM FlagTDC ValDimGray 12 8 ChipID Hit channel register 16 x 36 x 1 bits TDC ramp StartRampTDC BCID 16 x 8 bits ADC ramp Startrampb (wilkinson ramp) 16 ValidHoldAnalogb RazRangN 16 ReadMesureb Rstb Clk40MHz SlowClock StartAcqt StartConvDAQb StartReadOut NoTrig RamFull TransmitOn OutSerie EndReadOut Chipsat

11. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 11 SPIROC layout 36 8bit 5V DAC Dual DACBandgap 36*16 Analog memory 36 Preamp Shaper discri 36*2 Wilkinson ADC SRAM Readout

12. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 12 High gain Preamplifier response Low gain Preamplifier response Fast shaper High gain Slow shaper Low gain Slow shaper Tp=15ns Tp=50ns Noise/pe ratio = 25 Noise/pe ratio = 11 Noise/pe ratio = 3 1mV/pe 10mV/pe 120mV/pe Simulation obtained with SiPM gain = 10 6 _ 1 pe = 160 fC Simulated waveforms

13. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 13 Input DAC 8 bit, 5V range LSB=20mV 36 DACs : one per channel Ultra low power (1µW) : no power pulsing Can sink 10 µA leakage current Linearity : ± 2%

14. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 14 Trigger and gain select DAC meas. Linearity : typ ±0.2% Residuals (V) Linearity Trigger DAC Gain selection DAC

15. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 15 Input preamp Bi-gain low noise preamp –Reused from SKIROC –Low noise charge preamp capacitively coupled = voltage preamp –Gain adjustable with 4 bits common to all preamps : Cf=0.2, 0.4, 0.8, 1.6 pF –Positive input pulse –8 mV/pe in HI Gain –Noise : 1.4 nV/sqrt(Hz) –Power : 2 mW (unpulsed) Low gain at preamp level –1.5pF coupling capacitor –0.8 mV/pe, MAX : 2000 pe (300pC) 15pF 0.1pF-1.5pF +HV Si PM 8-bit DAC ASIC High voltage on the cable shielding

16. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 16 Analog waveforms 680fC ( ~4 pe @SiPM gain=10 6) in SPIROC Charge measurement Auto trigger High gain channel output Vout=30mV Noise=1mV Gain=45mV/pC pe/noise~7 (expected ~11) Set up: Cf=400fF Tau=50ns

17. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 17 Gain uniformity Pedestal uniformity –Avg = 1.16V –Rms = 1.8 mV Gain uniformity –Rms 1% –45 mV/pC (Cf=0.2pF tau=50ns) Noise : ~ 1mV

18. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 18 S-curves Trigger efficiency versus Threshold (1UDAC=2mV) Measured Noise ~8mV (expected ~ 5mV)

19. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 19 Trigger linearity

20. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 20 Crosstalk and trigger time walk Very low Cross-Talk : 0.3% (long distance cross talk due to slow shaper voltage reference: If this voltage decoupled with 100µF, it becomes negligible ~0.04%) Trigger time walk: ~10ns

21. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 21 12 bit Wilkinson ADC performance (stupid) bug in internal ADC : cannot be tested Similar to ADC in sister chip SKIROC 1 ADC/channel 12 bits 80µs Fixed in SPIROC2 Noise in low gain shaper rms = 0.9UADC (330µV) MIP = 3 UADC 1050 1080 Noise in high gain shaper rms = 4UADC (1.4mV) MIP= 30UADC Pedestal value vs Channel number

22. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 22 Single photoelectron spectrum Spiroc1 can already replace FLC_SiPM (multiplexed analog output) ©B. Lutz (DESY)

23. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 23 Conclusion SPIROC is a versatile readout chip for SiPM photodetectors It provides –Charge measurement from 1 pe to 2000 pe in two linear scales with a signal to noise ratio of 10 –Time measurement to better than 1 ns –Auto-trigger on ½ pe with internal 10 bit DAC –Ultra low power 5V 8bit input DAC for SiPM gain adjustment –25 µW/ch with 1% ILC Power pulsing –On chip Wilkinson ADC and RAM for daisy chain readout It will be produced in large scale in 2009 for the EUDET AHCAL module More information on MAROC, HaRDROC, SPIROC, SKIROC, PARISROC on http://omega.in2p3.fr

24. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 24 Backup slides

25. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 25 Barrel HCAL architecture AHCAL Slab 6 HBUs in a row HBU HCAL Base Unit 12 x 12 tiles SPIROC 4 on a HBU HEB HCAL Endcap Board Hosts mezzanine modules: DIF, CALIB and POWER HLD HCAL Layer Distributor 1/16 of barrel half Power: 40 µW / channel Heat: T grad. 0.3K/2m Time constant: 6 d P.Goettlicher (DESY) Front end ASICs embedded Interfaces accessible

26. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 26 Integrated layer design Sector wall Reflector Foil 100µm Polyimide Foil 100µm PCB 800µm Bolt with inner M3 thread welded to bottom plate SiPM Tile 3mm HBU Interface 500µm gap Bottom Plate 600µm ASIC TQFP-100 1mm high Top Plate 600µm steel Component Area: 900µm high HBU height: 6.1mm (4.9mm without covers => absorber) Absorber Plates (steel) Spacer 1.7mm Top Plate fixing DESY integrated M.Reinecke (DESY)

27. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 27 Slow shaper & SCA Slow shaper from HaRDROC –Variable peaking time : 50-150 ns –3 bits common to all channels –High Gain = 10 mV/pe –Noise = 900 µV –Low gain = 1 mV/pe Backup : analog T&H from HaRDROC –Hold capacitor : 2pF -> 0.5 pF –Needs external hold signal –Multiplexed analog output @ 5MHz –Allows readout with DAQ0 SCA : new block –= multiple T&H –Depth = 16 –Droop < 1 mV/ms (measured on HaRDROC) –Hold signal generated internally with adjustable delay (new block) 50 -100ns Slow Shaper Depth 16 Analog memory

28. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 28 TDC New block –12 bits –300 ns full scale –100 ps LSB (not accuracy !) –« common start » = BC –Time stored in SCA together with charge –Can also be readout with backup analog T Fast ramp 300ns Trigger Depth 16 Discri

29. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 29 Wilkinson ADC Taken from MAROC –New : adjustable resolution : 8 - 10 or 12 bits –40 MHz clock –6-100 µs conversion time –Power dissipation : 350µW

30. 16 sep 08 J. Fleury - SPIROC : SiPM readout ASIC TWEPP 2008 - Naxos 30 Digital part Inspired from HaRDROC –Internal or external Trigger –OR36 output –Discriminator Validation fast input –4kbyte RAM –« Open collector » output signals –LVDS clocks –Start conversion –Start/end readout