1. ECE 448 – FPGA and ASIC Design with VHDL George Mason University ECE 448 Lab 1 Implementing Combinational Logic in VHDL

2. Part 1: General Lab Rules Part 2: Introduction to Experiment 1: ALU of MIPS Part 3: Hands-on Session: Simulation and Synthesis in the Aldec Active HDL Environment Agenda for today

3. Part 1 General Lab Rules

4. See the Rules posted at the Course Web Page. Follow this link.this link

5. Part 2 Introduction to Experiment 1 ALU of MIPS

6. Overview of MIPS datapath Source: Source: http://cseweb.ucsd.edu/~carter/141/c09oneCycle.pdf

7. MIPS overview 32 bit addresses 32 registers/5 bit register addresses 3 basic types of instructions  Register (R) -type  Immediate (I)-type  Jump (J)-type

8. R-type Instruction Format opcode: 6 bit field identifying the instruction. For all R-type instructions field is “000000”. Rs: 5 bit field identifying the first source register for the operation. Rt: 5 bit field identifying the second source register. Rd: 5 bit field identifying the destination register for the operation. shamt: the shift amount for any shift operation. func: A more specific function operation code, i.e., add, subtract. opcodeRsRtRdshamtfunc

9. I-type Instruction Format opcode: 6 bit field identifying the instruction. Rs: 5 bit field identifying the source register for the operation. Rt: 5 bit field identifying the destination register. Imm: 16 bit immediate value for this operation. opcodeRsRtImm

10. J-type Instruction Format opcode: 6 bit field identifying the instruction; either 0x02 (JUMP) or 0x03 (Jump And Link, JAL) address: 26 bit address to jump to opcodeaddress

11. Instructions to Implement Required R-type ADD AND OR SUB XOR SLT (Set Less Than) SLTU (Set Less Than Unsigned) I-Type ADDI ANDI ORI

12. Instructions to Implement Extra Credit R-type SLL (Shift Left Logical) SRL (Shift Right Logical) SLLV (Shift Left Logical Variable) SRLV (Shift Right Logical Variable)

13. Block Diagram Behavioral

14. Required Tasks Example of a Similar Problem Mini ALU

15. opcode A B M R Mini ALU 4 4 4 4 4

16. MnemonicOperationOpcode ADDABR= A + B0000 ADDAMR = A + M0001 SUBABR = A - B0010 SUBAMR = A - M0011 NOTAR = NOT A0100 NOTBR = NOT B0101 NOTMR = NOT M0110 ANDABR = A AND B0111 ANDAMR = A AND M1000 ORABR = A OR B1001 ORAMR = A OR M1010 XORABR = A XOR B1011 XORAMR = A XOR M1100

17. Block diagram

18. Unsigned and Signed Arithmetic in VHDL

19. 19ECE 448 – FPGA and ASIC Design with VHDL Operations on Unsigned Numbers For operations on unsigned numbers USE ieee.numeric_std.all and signals of the type UNSIGNED and conversion functions: std_logic_vector(), unsigned() OR USE ieee.std_logic_unsigned.all and signals of the type STD_LOGIC_VECTOR (recommended) (permitted)

20. 20ECE 448 – FPGA and ASIC Design with VHDL Operations on Signed Numbers For operations on signed numbers USE ieee.numeric_std.all, signals of the type SIGNED, and conversion functions: std_logic_vector(), signed() OR USE ieee.std_logic_signed.all and signals of the type STD_LOGIC_VECTOR (recommended) (permitted)

21. 21ECE 448 – FPGA and ASIC Design with VHDL Signed and Unsigned Types Behave exactly like STD_LOGIC_VECTOR plus, they determine whether a given vector should be treated as a signed or unsigned number. Require USE ieee.numeric_std.all;

22. 22ECE 448 – FPGA and ASIC Design with VHDL Multiplication of unsigned numbers LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all ; entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); c : out STD_LOGIC_VECTOR(15 downto 0) ); end multiply; architecture dataflow of multiply is c <= a * b; end dataflow;

23. 23ECE 448 – FPGA and ASIC Design with VHDL Multiplication of signed numbers LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all ; entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); c : out STD_LOGIC_VECTOR(15 downto 0) ); end multiply; architecture dataflow of multiply is c <= a * b; end dataflow;

24. 24ECE 448 – FPGA and ASIC Design with VHDL Multiplication of signed and unsigned numbers LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all ; entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); cu : out STD_LOGIC_VECTOR(15 downto 0); cs : out STD_LOGIC_VECTOR(15 downto 0) ); end multiply; architecture dataflow of multiply is begin -- signed multiplication cs <= STD_LOGIC_VECTOR(SIGNED(a)*SIGNED(b)); -- unsigned multiplication cu <= STD_LOGIC_VECTOR(UNSIGNED(a)*UNSIGNED(b)) end dataflow;

25. Extra Credit Example of a Similar Problem Variable Rotator

26. Function C = A <<< B A – 4-bit data input B – 2-bit rotation amount

27. Interface 4 4 2 A B C

28. Block diagram C

29. Fixed Rotation in VHDL A(3) A(2) A(1) A(0) A(2)A(1)A(0)A(3) A<<<1 SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL ArotL: STD_LOGIC_VECTOR(3 DOWNTO 0); ArotL <= A(2 downto 0) & A(3); ArotL A

30. Part 3 Hands-on Session Simulation and Synthesis in the Aldec Active HDL Environment

31. Example for the Hands-on Session MLU Block Diagram B A NEG_A NEG_B IN0 IN1 IN2 IN3 OUTPUT SEL1 SEL0 MUX_4_1 L0L1 NEG_Y Y Y1 A1 B1 MUX_0 MUX_1 MUX_2 MUX_3 0101 0101 0101