1. Adapted from Computer Organization and Design, Patterson & Hennessy, UCB ECE232: Hardware Organization and Design Part 10: Control Design http://www.ecs.umass.edu/ece/ece232/

2. ECE232: MIPS Control 2 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren Datapath With Control

3. ECE232: MIPS Control 3 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren R-Format Instruction: add $t1, $t2, $t3

4. ECE232: MIPS Control 4 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren Load Instruction InstructionRegDstALUSrc Memto- Reg Write Mem Read Mem WriteBranchALUOp1ALUp0 lw011110000

5. ECE232: MIPS Control 5 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren Branch-on-Equal Instruction InstructionRegDstALUSrc Memto- Reg Write Mem Read Mem WriteBranchALUOp1ALUp0 beqx0x000101

6. ECE232: MIPS Control 6 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren Simple combinational logic Src MemtoReg RegWrite MemRead MemWrite Branch ALUOp1 ALUOpO InstructionRegDstALUSrc Memto- Reg Write Mem Read Mem WriteBranchALUOp1ALUp0 R-format100100010 lw 011110000 sw X1X001000 beq X0X000101

7. ECE232: MIPS Control 7 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren Single-Cycle Machine: Appraisal  All instructions complete in one clock cycle (CPI = 1)  Some instructions take more steps than others lw is most expensive (5 steps, vs. 4 for R-type and sw, 3 for beq)  Clock cycle must cover longest instruction  inefficient suppose mult is added? 32-shift/add steps  would delay every other instruction

8. ECE232: MIPS Control 8 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren Cycle time and speedup computation  Assume: 2ns for instruction/data memory 1ns for decode/register read 2ns for ALU and 1ns for register write  Single-cycle datapath clock period = 8ns  Assume an instruction mix of 24% loads, 12% stores, 44% R-format, 18% branches, and 2% jumps  Assuming a variable-cycle datapath, average clock period = 8*0.24+7*0.12+6*0.44+5*0.18+3*0.02=6.36 ns  Possible Speed-up = 1.26

9. ECE232: MIPS Control 9 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren Multicycle Implementation (MIPS-lite v.2)  Want more efficient implementation  Each step will take one clock cycle (not each instruction) [CPI > 1] shorter clock cycle: cycle time constrained by longest step, not longest instruction simpler instructions take fewer cycles higher overall performance  More complex control: finite state machine  Versatile (can extend for new instructions: swap, mult-add etc.)

10. ECE232: MIPS Control 10 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren Clocking: single-cycle vs. multi-cycle add $t0,$t1,$t2 beq $t0,$t1,L Single-cycle Implementation Multicycle Implementation add $t0,$t1,$t2 beq $t0,$t1,L Multicycle Implementation: less waste=higher performance waste clock

11. ECE232: MIPS Control 11 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren How fast can we run the clock?  Depends on how much we want to be done per clock cycle Can do: several “inexpensive” datapath operations per clock simple gates (AND, OR, …) single datapath registers (PC) sign extender, left shifter, multiplexor OR: exactly one “expensive” datapath operation per clock ALU operation Register File access (2 reads, or 1 write) Memory access (read or write)

12. ECE232: MIPS Control 12 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren Multicycle Datapath (overview) Registers Read Reg1 ALUALU Read Reg2 Write Reg Data PCPC Address Instruction or Data Memory MIPS-lite Multicycle Version A B ALU- Out Instr- uction Register Data Memory Data Register Read data 1 Read data 2 One ALU (no extra adders) One Memory (no separate IMem, DMem) New Temporary Registers (“clocked”/require clock input)

13. ECE232: MIPS Control 13 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren Multicycle Implementation  Datapath changes one memory: both instructions and data (because can access on separate steps) one ALU (eliminate extra adders) extra “invisible” registers to capture intermediate (per- step) datapath results  Controller changes controller must fire control lines in correct sequence and correct time  controller must remember current execution step, advance to next step

14. ECE232: MIPS Control 14 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren Datapath + Control Points

15. ECE232: MIPS Control 15 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren MemRead ALUSrcA = 0 IorD = 0 IRWrite ALUSrcB = 1 ALUOp = 0 PCWrite PCSrc = 0 state 0 ALUSrcA = 0 ALUSrcB = 3 ALUOp = 0 ALUSrcA = 1 ALUSrcB = 2 ALUOp = 0 ALUSrcA = 1 ALUSrcB = 0 ALUOp =2 ALUSrcA = 1 ALUSrcB = 0 ALUOp =1 PCWriteCond PCSrc = 1 1 2 6 8 Memory Access R-format execution Branch Completion FSM diagram for multi-cycle machine start new instruction cycle 1 cycle 2 cycle 3 lw/sw R-format beq

16. ECE232: MIPS Control 16 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren MemRead IorD = 1 MemWrite IorD = 1 RegDst = 1 RegWrite MemtoReg = 0 RegDst = 0 RegWrite MemtoReg = 1 write-back (step 5) memory access (step 4) memory access (step 4) R-format completion (step 4) 3 5 7 4 from state 2 to state 0 FSM controller: execution cycles 3-5 lw sw from state 6 cycle 4 cycle 5

17. ECE232: MIPS Control 17 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMass Koren Cycle 1 MemRead ALUSrcA = 0 IorD = 0 IRWrite ALUSrcB = 1 ALUOp = 0 PCWrite PCSrc = 0 Cycle 1