1. 15-Aug-08DoE Site Review / Harvard(1) Front End Electronics for the NOvA Neutrino Detector John Oliver, Nathan Felt, Sarah Harder Long baseline neutrino experiment Fermilab (Chicago) to northern Minnesota (~800 km) ~15 kTon “Far” and smaller “Near” detectors

2. 15-Aug-08DoE Site Review / Harvard(2) Electronics & DAQ Organization L2 Manager – L. Mualem / UC Electronic Project Engineer – J. Oliver / Harvard Front End Boards (FEBs)  L3 Manager – J. Oliver  Elect Eng – N. Felt  Technician / designer – S. Harder  Test software – J. Boehm, S. Cavanaugh DAQ, Timing – FNAL ASIC development – T. Zimmerman, FNAL Power Distribution & Slow Controls – UVa

3. 15-Aug-08DoE Site Review / Harvard(3) Readout Hierarchy ~12,000 Front End Boards (~ 1 FEB per 1.2 tons of NOvA detector) running synchronously Each “hit”  timestamp synched to Global timing system + pulseheight Global timing system with GPS receiver to correlate timing with NUMI beam spills All data are buffered for ~ 10 seconds awaiting spill window information from NUMI beam line DCM DAQ & Timing FEB GPS Receiver

4. 15-Aug-08DoE Site Review / Harvard(4) DAQ Heirarchy – 64 FEBs to one “Data Concentrator Power Distribution Power Distribution Data Concentrator Data Concentrator FEBs Beam DAQ

5. 15-Aug-08DoE Site Review / Harvard(5) Front End Board (FEB) Architecture APD Module TE Cooler Control ADC FPGA DAQ ASIC Thermoelectric cooler maintains – 15C at APD ASIC integrates & shapes 32 signal channels from APD Selectable risetime & falltime constants ASIC’s 8:1 Multiplexers run @ 16 MHz to sample each channel at 500 ns/sample ASIC’s four outputs are continuously digitized by quad ADC @ 16 Msps and sent to FPGA ~ 12,000 FEBs in NOvA Far Detector

6. 15-Aug-08DoE Site Review / Harvard(6) TfTf TrTr 8:1 Mux TfTf TrTr TfTf TrTr TfTf TrTr 8 8 8 8 32 ch NOvA ASIC (T. Zimmerman / FNAL) 16 MHz multiplexers 2 Msps per channel Adjustable risetime & falltime Status  Prototypes fabricated on TSMC 0.25u CMOS  Tested & work as per simulations  2 nd version now available to work at either Near or Far detectors.

7. 15-Aug-08DoE Site Review / Harvard(7) Signal Processing Use multiple correlated pairs of samples centered on leading edge Separate DSP filters in FPGA (firmware) for  Pulseheight  Timing  Triggering

8. 15-Aug-08DoE Site Review / Harvard(8) Summary & Status of NOvA FEB Flexible architecture : Continuous digitization + DSP  2 MSPS DSO on every channel (Far Detector): Local DSP filters in FPGA  Up to 8 MSPS for use in Near Detector (resolve event overlaps) FEB Version 2.0 successfully tested in FY06-07 FEB Version 3.0  Works with NOvA ASIC V2.0  Design completed Jan 08  Project halted due to funding  Prototypes to be produced September 08  Testing FY 09  To be used on IPND – Schedule TBD FEB V4.0  May not be necessary if V3.0 meets all specs. (Minor changes to V3.0  V3.1)

9. 15-Aug-08DoE Site Review / Harvard(9) FEB V3.0