1. MIPS Processor

2. Registers in MIPS In MIPS, there are 32 Registers.
We need read up to two registers, and write to up to one register.
Think registers as D flip-flops. Each register has 32 Dffs.
The control signals are:
readReg1, readReg2: 5 bits. Used to specify which reg to read.
writeReg: 5-bits. Used to specify which reg to write.
Data: if write, what data should be written into the reg.
RegWrite: whether to write or not.

3. This is for read.

4. To write to a register The data is connected to every register.
Use RegWrite, generate a ``LOAD’’ signal for the register you want to write to.
Every register has a LOAD signal. If that signal is `1’, new data will be set.
Only the target register’s LOAD signal is `1’.

5. RAM

6. A RAM Example RAM. Control signals:
address: If write, which location to write to. If read, which location to read from.
Chip select: whether to use this chip or not.
Output enable: whether to enable output (output some voltage or in high-impedence state)
Write enable: whether to read or write.
Din: if write, what data should be written into the location specified by address.
Assume that there is a RAM with only 2 address lines and two bit data lines. How many bits can it hold?
11/8/ :04:17 AM
week11-5.ppt

7. The processor We now know all the parts in the processor.
ALU PC
Register file
Also
RAM
How to put them together? How to make them execute an instruction as we need?

8. ALU

9. The execution of an instruction
First we need to fetch the instruction at the address given by the current PC from instruction memory
Then we need to decode the instruction
Based on the instruction, we need to do accordingly
For sequential instructions, we then go the next instruction by increasing the PC. For jump and branch instructions, PC will be changed

10. Basic MIPS Implementation
We will focus on design of a basic MIPS processor that includes a subset of the core MIPS instruction set
The arithmetic-logic instructions add, sub, and, or, and slt
The memory-reference instructions load word and store word
The instructions branch equal and jump
11/18/2007 7:39:36 PM
week13-1.ppt

12. MIPS Implementation Overview
For every instruction, the first two steps are identical
Fetch the instruction from the memory according to the value of the program counter
Read one or two registers (using fields of instructions to select the registers)
For load word, we need to read only one register
Most other instructions (except jump) require we read two registers
After the two steps, the actions required depend on the instructions
However, the actions are similar
11/18/2007 7:39:36 PM
week13-1.ppt

13. Instruction Fetch and PC Increment
Since for every instruction, the first step is to fetch the instruction from memory
In addition, for most instructions, the next instruction will be at PC + 4
11/18/2007 7:39:38 PM
week13-1.ppt

14. R-type Instructions Also called arithmetic-logical instructions
Including add, sub, and, or, and slt
Each one reads from two registers, performs an arithmetic or logical operation on the registers, and then write the result to a register
11/18/2007 7:39:38 PM
week13-1.ppt

15. R-type Instructions
Suppose the instruction is add $t0, $t1, $t2, what are the read reg1, read reg2, and write reg? What is the value of RegWrite? How to control the ALU to do add?
11/15/2007 5:02:08 PM
week-13-3.ppt

16. Datapath only for R-type instructions

17. Datapath only for R-type instructions (Answer)

18. Data Transfer Instructions
Load word and store word instructions have the following general form
lw $rt, offset_value($rs)
opcode (6 bits) rs (5 bits) rt (5 bits) offset (16 bits)
sw $rt, offset_value($rs)
They need to compute a memory address by adding the base register to the sign-extended 16-bit offset ()
11/15/2007 5:02:10 PM
week-13-3.ppt

19. Load
For instruction load $t0, 16($t1), what should the control signal be?
RegWrite = 1
ALUOp = add code

20. Data path
Do both lw and sw, and ask for student participation

21. Data path only for lw (answer)

22. Data path only for sw (answer)

23. Branch Instruction
Beq has three operands, two registers that are compared for equality and a 16-bit offset used to compute the branch-target address
beq $rs, $rt, offset
opcode (6 bits) rs (5 bits) rt (5 bits) offset (16 bits)
Note that the 16-bit offset is given in terms of instructions, not bytes and is relative to PC + 4
11/18/2007 7:39:42 PM
week13-1.ppt

24. Designing a processor only for beq
Are these enough? How many adders do we need? How to do the selection?

25. Designing a processor only for beq

26. Designing a processor only for beq (answer)
11/18/2007 7:39:43 PM
week13-1.ppt