1. ©2000 Addison Wesley Little- and big-endian memory organizations

2. ©2000 Addison Wesley ARM operating modes and register usage.

3. ©2000 Addison Wesley Exception vector addresses

4. ©2000 Addison Wesley The ARM condition code field

5. ©2000 Addison Wesley ARM condition codes

6. ©2000 Addison Wesley Branch and Branch with Link binary encoding

7. ©2000 Addison Wesley Branch (with optional link) and exchange instruction binary encoding condRm 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 31282765430 1L 1 1 1 0 1H 24-bit signed word offset 3128272524230 (1) BX|BLX Rm (2) BLX label

8. ©2000 Addison Wesley Software interrupt binary encoding

9. ©2000 Addison Wesley Data processing instruction binary encoding cond0 operand 2 #opcodeSRnRd 312827262524212019161512110 destination register first operand register set condition codes arithmetic/logic function 8-bit immediate 1 2511870 #rot Rm 11765430 #shift Rm 0 25 118765430 Rs Sh 0 10 immediate alignment immediate shift length shift type second operand register register shift length

10. ©2000 Addison Wesley ARM data processing instructions

11. ©2000 Addison Wesley Multiply instruction binary encoding

12. ©2000 Addison Wesley Multiply instructions

13. ©2000 Addison Wesley Count leading zeros instruction binary encoding

14. ©2000 Addison Wesley Single word and unsigned byte data transfer instruction binary encoding

15. ©2000 Addison Wesley Half-word and signed byte data transfer instruction binary encoding

16. ©2000 Addison Wesley Data type encoding

17. ©2000 Addison Wesley Multiple register data transfer instruction binary encoding

18. ©2000 Addison Wesley Swap memory and register instruction binary encoding

19. ©2000 Addison Wesley Status register to general register transfer instruction binary encoding

20. ©2000 Addison Wesley Transfer to status register instruction binary encoding cond0 operand #field1 1 3128272625242322212019161512110 field mask 8-bit immediate1 2511870 Rm 11430 0 25 0 0 0 0 operand register 1 0R SPSR/CPSR #rot immediate alignment

21. ©2000 Addison Wesley Coprocessor data processing instruction binary encoding

22. ©2000 Addison Wesley Coprocessor data transfer instruction binary encoding

23. ©2000 Addison Wesley Coprocessor register transfer instruction binary encoding

24. ©2000 Addison Wesley Breakpoint instruction binary encoding

25. ©2000 Addison Wesley Arithmetic instruction extension space

26. ©2000 Addison Wesley Control instruction extension space

27. ©2000 Addison Wesley Data transfer instruction extension space

28. ©2000 Addison Wesley Coprocessor instruction extension space

29. ©2000 Addison Wesley Undefined instruction space

30. ©2000 Addison Wesley Summary of ARM architectures Core Architecture ARM1 v1 ARM2 v2 ARM2as, ARM3 v2a ARM6, ARM600, ARM610 v3 ARM7, ARM700, ARM710 v3 ARM7TDMI, ARM710T, ARM720T, ARM740T v4T StrongARM, ARM8, ARM810 v4 ARM9TDMI, ARM920T, ARM940T v4T ARM9ES v5TE ARM10TDMI, ARM1020E v5TE