1. 林仲祥, 李苡嬋 CSIE, NTU 11 / 03, 2008 Simplescalar: Victim Cache 1 ACA2008 HW3

2.  ISCA’90 (Norman P. Jouppi) “Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers” Victim Cache 2

3. General cache Victim cache data Hit Data Miss Data Search Victim miss data Memory (or lower cache)

4. Victim Cache General cache Victim cache data Miss Data Search Victim miss data Memory (or lower cache) data

5. Victim Cache General cache Victim cache data Miss Data Search Victim miss data Memory (or lower cache) data LRU

6. Victim Cache General cache Victim cache data Miss Data Search Victim hit Memory (or lower cache) data

7. HW3 How To  Implement by SimpleScalar

8.  Cache Software Architecture 8 cache.c / cache.h

9.  D-Cache L1 Hardware Architecture 9 loadstore

10.  ruu_issue(); for loads, first scan LSQ to see if a store forward is possible, if not, access the data cache.  ruu_commit(); stores must retire their store value to the cache at commit. sim-outorder.c 10 load store

11.  cache_create(); create and initialize a general cache structure  cache_access(); access a cache cache.c 11

12.  Check all cache parameters  Allocate the cache structure  Initialize user parameters  Initialize cache stats  Allocate data blocks cache.c: cache_create(); 12

13.  Check for a hit Fast hit  access to same block Hit  access cache  update dirty (write hit)  update list by LRU policy Miss  select the appropriate block to replace  write back replaced block data  read data block  update block tags  update dirty status (if cmd = write) cache.c: cache_access(); 13

14. Other information…  Most modifications in this homework: cache.c cache.h  Cache configuration (refer to hack_guide.pdf) : : : : Ex. dl1:8:32:2:l  Name = dl1  # of set = 8  Block size = 32 bytes  # of way = 2  Replacement policy = LRU 14 # of set = 8 # of way (assoc) = 2 block size = 32 bytes