1. CERN Feb 3, 2009 Electronics User Group meeting 24 Jan 18-22, 2009A. Kluge http://electronics-user-group.web.cern.ch/electronics-user-group/

2. Agenda Introduction (10’), Alex Kluge Introduction (10’), Alex Kluge News from IT – Cadence/PCB/simulation Design flow (30') John Evans, Pierre Bähler News from IT – Cadence/PCB/simulation Design flow (30') John Evans, Pierre Bähler News of Cadence design flow discussion in PH-ESE(15’), Alex News of Cadence design flow discussion in PH-ESE(15’), Alex News from EN-ICE (former TS-DEM) - News, new structure (30') Betty Magnin, (excused) News from EN-ICE (former TS-DEM) - News, new structure (30') Betty Magnin, (excused) Discussion on review processes (20’), Tullio Grassi Discussion on review processes (20’), Tullio Grassi New tool/IP core requests (10'), all New tool/IP core requests (10'), all AOB (10') AOB (10') Feb 3, 2009A. Kluge

3. Introduction Andrea Boccardi as representative of the BE-BI-QP team will replace Jean Jacques Savioz Andrea Boccardi as representative of the BE-BI-QP team will replace Jean Jacques Savioz Gianluca Agieri Rinella, Csaba Soos, Paschalis Vichoudis, PH-ESE Gianluca Agieri Rinella, Csaba Soos, Paschalis Vichoudis, PH-ESE Tullio Grassi, CMS, CERN user Tullio Grassi, CMS, CERN user Janos Ero, CMS, CERN user Janos Ero, CMS, CERN user Jan 18-22, 2009A. Kluge

4. Report on design flow test does not exist on Windows anymore

5. Report on design flow test Simulation (nclaunch) tested for verilog and VHDL under linux on lxplus & PARC Simulation (nclaunch) tested for verilog and VHDL under linux on lxplus & PARC for me: grahical interface considerably faster for me: grahical interface considerably faster both verilog & VHDL simulation are working both verilog & VHDL simulation are working DFS file access to lxplus/Cadence not working DFS file access to lxplus/Cadence not working Solution: strore files on AFS and access files from PC via OpenAfs -> working Solution: strore files on AFS and access files from PC via OpenAfs -> working AFS space can be created by IT dedicated to each CAE user AFS space can be created by IT dedicated to each CAE user Jan 18-22, 2009A. Kluge

6. PH-ESE meeting on design flow The aim of the meeting was to define a CAE design flow suitable for the work in the PH-ESE group. The aim of the meeting was to define a CAE design flow suitable for the work in the PH-ESE group. Feb 3, 2009A. Kluge

7. PH-ESE meeting on design flow Elaborate simulation environment needs to be used to provide efficient results. Elaborate simulation environment needs to be used to provide efficient results. test bench based FPGA simulations, where also the connections to other components on the board (memories, other FPGAs) are simulated in a simplified manner. test bench based FPGA simulations, where also the connections to other components on the board (memories, other FPGAs) are simulated in a simplified manner. board level simulations where the FPGAs are simulated both functionally and with timing back annotations together with a HDL description of the PCB board. The PCB board simulation is used either to verify the proper connections between components on the board (FPGA, RAMs, active and passive components) or components on other boards.In critical cases the timing information of the board layout is back annotated to the simulation. board level simulations where the FPGAs are simulated both functionally and with timing back annotations together with a HDL description of the PCB board. The PCB board simulation is used either to verify the proper connections between components on the board (FPGA, RAMs, active and passive components) or components on other boards.In critical cases the timing information of the board layout is back annotated to the simulation. system level simulations where all components of a system including the front-end ASIC, the communication links, the back-end electronics with several different FPGAs and the DAQ, DCS and trigger interfaces are simulated. This is done in a multi designer environment where the simulation is composed of several designs which are actively developed simultaneously. system level simulations where all components of a system including the front-end ASIC, the communication links, the back-end electronics with several different FPGAs and the DAQ, DCS and trigger interfaces are simulated. This is done in a multi designer environment where the simulation is composed of several designs which are actively developed simultaneously. Feb 3, 2009A. Kluge

8. PH-ESE meeting on design flow Cadence design flow together on the same platform as this allows cross selecting signal for different tools, such as graphically selecting signals in the schematic for display in the simulator, or selecting signals in the layout. As a result the schematic entry, the simulator and the layout tool must run on the same platform. Cadence design flow together on the same platform as this allows cross selecting signal for different tools, such as graphically selecting signals in the schematic for display in the simulator, or selecting signals in the layout. As a result the schematic entry, the simulator and the layout tool must run on the same platform. Thus the proposed solution of having only the simulator running under Linux and exchanging the files via AFS does therefore not work. Thus the proposed solution of having only the simulator running under Linux and exchanging the files via AFS does therefore not work. Furthermore in view of the faster communications between FPGAs and boards and higher complexity board level simulations will increase in importance. Furthermore in view of the faster communications between FPGAs and boards and higher complexity board level simulations will increase in importance. Feb 3, 2009A. Kluge

9. PH-ESE request for Cadence Flow lxplus PARC machines and personal Linux PC personal Windows PC personal installation or terminal server personal Windows PC or terminal server B1

10. PH-ESE preliminary conclusion In conclusion PH-ESE would like to request the Cadence SPB and Cadence IUS design kits to be available on Linux as priority with SPB installations on windows available. In conclusion PH-ESE would like to request the Cadence SPB and Cadence IUS design kits to be available on Linux as priority with SPB installations on windows available. Concerning the FPGA design tools (XILINX, ALTERA,....) the PH-ESE users stated that running the software on a single platform as the Cadence tools is preferable. However, for on- site FPGA programming a windows computer platform is preferred. In conclusion, it would be acceptable if the main installation platform for these tools is Windows. Also, PH-ESE would request to allow private installation of these tool also on Linux PC, if possible also on the lxplus/PARC cluster. Concerning the FPGA design tools (XILINX, ALTERA,....) the PH-ESE users stated that running the software on a single platform as the Cadence tools is preferable. However, for on- site FPGA programming a windows computer platform is preferred. In conclusion, it would be acceptable if the main installation platform for these tools is Windows. Also, PH-ESE would request to allow private installation of these tool also on Linux PC, if possible also on the lxplus/PARC cluster. Jan 18-22, 2009A. Kluge

11. Software tools Linkcad Linkcad Il est très pratique pour nous car il permet de transformer très rapidement des fichiers GDS en Gerber ou DXF et d’importer ces fichiers Il est très pratique pour nous car il permet de transformer très rapidement des fichiers GDS en Gerber ou DXF et d’importer ces fichiers Pour la création de composant dans allegro depuis un ASIC de CERN micro-electronique Pour la création de composant dans allegro depuis un ASIC de CERN micro-electronique Jan 18-22, 2009A. Kluge

12. linkCad Jan 18-22, 2009A. Kluge

13. linkCad Jan 18-22, 2009A. Kluge

14. http://electronics-user-group.web.cern.ch/electronics- user-group/ http://electronics-user-group.web.cern.ch/electronics- user-group/ February 3, 2009A. Kluge