1. joal 2006 HT:1 Em3 Digital Electronics Design 1 Lecture 3-4 Sequential VHDLChap 4

2. joal 2006 HT:1 Em3 Digital Electronics Design 2 Concurrent VHDL Signal assignment Think of signals as physical connections Syntax (VHDL –93) Signal assignment: ’ ’;’ Syntax (VHDL –93) Signal assignment with delay: ’ ’after’ 10 ’ns’ ’;’ The nature of hardware is parallel. A HDL must have features to describe the parallel behavior of hardware. In VHDL this is called ”concurrent VHDL”. NB ”after” can’t be synthesised and is dismissed by synthesiser. Examples: a<=’0’; a<=b after 10 ns; a<=b and c; a<=’0’, ’1’ after 20 ns, b after 30 ns;

3. joal 2006 HT:1 Em3 Digital Electronics Design 3 Concurrent VHDL. Delays Inertial delay (tröghets): Default in VHDL. Spikes are not propagated (if ’after’ is used). Often used in electronic component delays. Transport delay: Pulses are always propagated. Used for delay lines. Reject delay: Is used when spike filtering is not the same as the circuit delay (VHDL- 93). Inertial delay is ignorded by synthesis tools. Transport delay will give errors (often). 10 20 30 40 50 60 70 [ns] ab a b1 <= a inertial after 10 ns; b2 <= a transport after 10 ns; b3 <= a reject 4 ns inertial after 10 ns; b1 b2 b3 10 20 30 40 50 60 70 80 [ns] a

4. joal 2006 HT:1 Em3 Digital Electronics Design 4 Signals and variables Signals are used for concurrent execution. Signal assignment =1 delta time (or more if after is used). Signals are declared in the concurrent part of VHDL. Signals are used in the concurrent and the sequential part of VHDL. Signal assignment: signal_a <= ’1’; architecture signal temp, diff: std_logic; begin temp <= in; -- external diff <= temp – 2; T T+  TT+2  T in233 tempold_value23 diffold_value 0

5. joal 2006 HT:1 Em3 Digital Electronics Design 5 Signals and variables, cont’d Variables are used for sequential execution. Variable assignment takes no time. Variables are declared in the sequential part of VHDL. Variabless are used in the sequential part of VHDL. Variable assignment: variable_a := ’1’; process variable in, temp, diff: std_logic; begin temp := in; diff := temp – 2; end process; T T+  TT+ 2  T in233 temp233 diff011 The program is executed every  T!

6. joal 2006 HT:1 Em3 Digital Electronics Design 6 Signals and variables, cont’d p0: process begin wait for 10 ns; sum1<=sum1+1; sum2<=sum1+1; end process; p0: process begin wait for 10 ns; sum1:=sum1+1; sum2:=sum1+1; end process; Timesum1sum2 000 1000 10+  T 11 2011 20+  T 22 3022 30+  T 33 Timesum1sum2 000 1012 10+  T 12 2023 20+  T 23 3034 30+  T 34

7. joal 2006 HT:1 Em3 Digital Electronics Design 7 Signals and variables, cont’d Variables can only store temporary values inside a process, function or procedure. Variables can’t transfer information outside sequential part of VHDL. Signals must be used to transfer information. architecture behav of ex is signal x: std_logic; begin p0: process variable y: std_logic; begin y:=’1’; x<=’1’; end process; p1: process variable y: std_logic; begin if y=’1’ then… if x=’1’ then… end process; end behav; ”same” x not ”same” y

8. joal 2006 HT:1 Em3 Digital Electronics Design 8 Signals and variables process(clk) variable cnt: integer range 0 to 15; begin if clk’event and clk=’1’ then cnt:=0; for i in 0 to 15 loop -- only comb. logic if data(i)=’1’ then cnt:=cnt+1; -- must be variable end if; end loop; if cnt>8 then maj<=’1’; else maj<=’0’; end if; end process; Information can only be transferred by signals. Variables are used in algorithms that will be synthesised to comb. logic. Don’t use variables to create registers. Example: Majority decoder. When the number of ”ones” in a 16 bit vector, data, (e.g. a shift register) is more than 8 the signal maj is set to ’1’ otherwise to ’0’. for i in 0 to 15 loop -- only comb. logic if data(i)=’1’ then cnt:=cnt+1; -- must be variable end if; end loop;

9. joal 2006 HT:1 Em3 Digital Electronics Design 9 Sequential VHDL architecture rtl of ex is concurrent declaration part begin concurrent VHDL concurrent VHDL concurrent VHDL end; process(….) sequential declaration part begin sequential VHDL end process;

10. joal 2006 HT:1 Em3 Digital Electronics Design 10 Sequential VHDL. Process statement The concept comes from software. Processes are executed concurrently but inside processes there may be sequential constructs. Process states: Executing and Waiting. wait execute reset process begin …… end process; TT A process goes in a forever loop. A wait command or end (if sensitivity list is used) will set the process in Wait state. It takes one delta time,  T, to go through a process from begin to end.

11. joal 2006 HT:1 Em3 Digital Electronics Design 11 Sequential VHDL. Process statement Signals in sensitivity list will change process state from waiting to executing. process(a,b) begin c<=a and b; end process; sensitivity list (a,b) wait execute change in a or b

12. joal 2006 HT:1 Em3 Digital Electronics Design 12 Sequential VHDL. Process statement Signals in wait command will change process state from waiting to executing. process begin wait on a,b; c<=a and b; end process; wait execute change in a or b

13. joal 2006 HT:1 Em3 Digital Electronics Design 13 Sequential VHDL. Process statement Sensitivity list and wait can’t be used at the same time in a process. process(a,b) begin wait on a,b; c<=a and b; end process;

14. joal 2006 HT:1 Em3 Digital Electronics Design 14 Sequential VHDL. Combinational Process Combinational processes are intended to generate combinational logic. If simulation and hardware after synthesis shall correspond all input signals (used on the right side in assignments) must be in sensitivity list. If only combinational logic (no latches) shall be generated then all output signals must be assigned values every time the process is executed. process(a,b) begin c<= a and b; end process; ? & a b c process(a,b) begin if b=’1’ then c<= a; end if; end process; ? En a b c latch

15. joal 2006 HT:1 Em3 Digital Electronics Design 15 Sequential VHDL. Clocked Processes Clocked processes can be clocked by a common clock, i.e. they are synhronous. All signals that are assigned a value in a clocked process will result in a flip-flop. Variables that are read before they are assigned values will result in flip-flops. process begin wait until clk=’1’; dout<= din; end process; ? FF clk clk dindout

16. joal 2006 HT:1 Em3 Digital Electronics Design 16 Sequential VHDL. Clocked Processes If a signal is not assigned a value in a clocked processes, the signal will retain the old value. The synthesis will result in feedback of the utput signal via a multiplexor. This is good design. Compare this to gated clock. ? process begin wait until clk=’1’; if en=’1’ then dout<= din; end if; end process; FF clk clk d dout 0 mux 1 S en din

17. joal 2006 HT:1 Em3 Digital Electronics Design 17 Sequential VHDL. Clocked Processes Gated clocks will result in not testable designs. Fast circuits use balanced clock trees and gating is not possible. In a synchronous design the clock scew requirements are very hard. ? clk2<=clk and en; process begin wait until clk2=’1’; dout<= din; end process; FF clk clk2 dout & en din clk

18. joal 2006 HT:1 Em3 Digital Electronics Design 18 Sequential VHDL. Clocked Processes All logic caused by a signal assignment will end up on the ”left” of the flip-flops. (Block B1 in front of the flip-flop’s inputs). architecture rtl of ex is signal q, q1: std_logic; begin process(clk,reset) begin if reset=’1’ then q<=’0’; elsif clk’event and clk=’1’ then if en=’1’ then q<=… -- boolean express. B1 end if; end process; q1<=q and … -- boolean expr. B2 end rtl; FF clk clk d q reset & & en & & B1 B2 q1 q<=… -- boolean express. B1 q1<=q and.. -- boolean expr. B2 The block B2 shall be in a combinational process or in the concurrent part. Several flip-flops can be in the same process, e.g. a shift register.

19. joal 2006 HT:1 Em3 Digital Electronics Design 19 Sequential VHDL. ”If” statement if then [elsif then ] [else ] end if; process(ssel,syn,a,b) begin if ssel=’0’ and syn=’1’ then sout<=a; else if ssel=’1’ and syn=’0’ then sout<=’0’; end if; end process; Compare ”when” in the concurrent part with ”if” in the sequential part.

20. joal 2006 HT:1 Em3 Digital Electronics Design 20 Sequential VHDL. ”Case” statement case is when => ; when => ; [when others => ]; end case; = [| ] process(sel,a,b,c) begin case sel is when ’0’ => c<=a; when ’1’=> c<=b; when others =>c<=’0’; end case; end process; Compare ”with” in the concurrent part with ”case” in the sequential part. includes ’U’, ’X’, ’H’,’L’,’W’ etc for std_logic All choices must be covered!!!

21. joal 2006 HT:1 Em3 Digital Electronics Design 21 Sequential VHDL. ”Case” statement signal a: std_logic_vector(1 downto 0); process(a) begin case a is when ”00” => q<=3; when ”01” | ”10” => q<=2; when others => q<=0; end case; end process; ”or” statement (vertical bar)

22. joal 2006 HT:1 Em3 Digital Electronics Design 22 Sequential VHDL. ”Case” statement signal a: integer; process(a) begin case a is when 0 | 1 => q<=3; when 1 to 17 => q<=2; when 23 downto 18 => q<=6; when others => q<=0; end case; end process; Range can be used but only for integers (numbers).

23. joal 2006 HT:1 Em3 Digital Electronics Design 23 Sequential VHDL. ”Case” statement signal a: std_logic_vector(7 downto 0); process(a) variable a_var: integer; Begin a_var:=conv_integer(a); case a_var is when 0 | 1 => q<=3; when 1 to 17 => q<=2; when 23 downto 18 => q<=6; when others => q<=0; end case; end process; Std_logic-vectors must be converted to integers if they shall be used in a range

24. joal 2006 HT:1 Em3 Digital Electronics Design 24 Sequential VHDL. ”Case” statement signal data: std_logic_vector(1 downto 0); process(data,a,b,c) begin case data is when ”00” => q<=a; when ”01” => q<=b; when others => q<=c; end case; end process; with-select in concurrent part is only a short form of corresponding process with case-when signal data: std_logic_vector(1 downto 0); with data select q<= a when ”00”, b when ”01”, c when others;

25. joal 2006 HT:1 Em3 Digital Electronics Design 25 Sequential VHDL. For loop statement Syntax [loop_label]: for in loop end loop [loop_label]; process(a,b,c) begin for i in 0 to 4 loop if a(i)=’1’ then q<=b(i); else q<=c(i); end if; end loop; end process; Notes: loop index may not be declared! loop index may not be changed inside the process! exit may be used to break the loop!

26. joal 2006 HT:1 Em3 Digital Electronics Design 26 Concurrent VHDL. Multiple assignments In the concurrent VHDL every assignment will generate a driver. Resolved data types as std_logic must be used. architecture rtl of ex is signal q: std_logic; begin q<=a when en_a=’1’ else ’H’; q<=b when en_b=’1’ else ’H’; end rtl; a en_a b en_b q

27. joal 2006 HT:1 Em3 Digital Electronics Design 27 Sequential VHDL. Multiple assignments In concurrent VHDL a driver is created for every signal assignment. In sequential VHDL only one driver is created for each signal and the value is overwritten. In this way a signal may be given a start value (default). process(a) begin q1<=’0’; q2<=’0’; case a is when ”00” => q1<=’1’; when ”11”=>q2<=’1’; end case; end process; default q2 q1

28. joal 2006 HT:1 Em3 Digital Electronics Design 28 Sequential VHDL. Multiple assignments Note that signals that are assigned values in two or more processes also will generate several drivers. Resolved data types must then be used. process(a) begin q<=’Z’; if a=”00” then q<=’1’; end process; process(a) begin q<=’Z’; if a=”11” then q<=’0’; end process; q<=’0’ when a=”11” else ’Z’; process(a) begin q<=’Z’; if a=”00” then q<=’1’; end process;

29. joal 2006 HT:1 Em3 Digital Electronics Design 29 Sequential VHDL. Wait statements There are four different ways to describe a wait statement in VHDL: process(a,b) -- sensitivity list wait until a=’1’; wait on a,b; wait for 10 ns; -- not for synthesis -- the process is -- executed once -- after reset. process(a,b) begin q<=a and b; end process; -- the process is -- executed once -- after reset. process begin q<=a and b; wait on a,b; end process; = -- the process is -- not executed -- before a or b is -- changed process begin wait on a,b; q<=a and b; end process; =

30. joal 2006 HT:1 Em3 Digital Electronics Design 30 VHDL has several attributes that can be used in simulation. In synthesis the ’event attribute is often used. examples of attributes for signals: if clk’event and clk=’1’ then -- clk has an edge. if a’stable(10 ns) then signal a: std_logic_vector(3 downto 0); --- for a’range loop -- a’range = 3 downto 0 examples of attributes for types: subtype my_type is integer range 15 downto 0; -- my_type’left = 15 -- my_type’right = 0; if clk’event and clk=’1’ then -- clk has an edge. Signal attributes

31. joal 2006 HT:1 Em3 Digital Electronics Design 31 Clock description in clocked processes -- Alt. 1. Main alternative process(clk) begin if clk’event and clk=’1’ then -- ’event is a predefined attribute q<=d; end if; end process; -- Alt. 2. process begin wait until clk=’1’; q<=d; end if; end process;

32. joal 2006 HT:1 Em3 Digital Electronics Design 32 Sequential VHDL. Asynchronous reset With asynchronous reset the flip-flops will be reset as soon as the reset signal is applied. process(clk,reset) begin if reset=’1’ then data=”00”; elsif clk’event and clk=’1’ then data<=data_in; end if; end process;

33. joal 2006 HT:1 Em3 Digital Electronics Design 33 Sequential VHDL. Synchronous reset With synchronous reset the flip-flops can only be reset at an active clock edge. Recommanded (by lecturer) way to write a clocked process with synchronous reset. process(clk) begin if clk’event and clk=’1’ then if reset=’1’ then data=”00”; else data<=data_in; end if; end process;

34. joal 2006 HT:1 Em3 Digital Electronics Design 34 If else is omitted in a when statement (VHDL-93) If a signal is not always assigned a value in a combinational process: Sequential VHDL. Latches Latches are created when: (normally they are not wanted!) process(enable, d_in) begin if enable=’1’ then q<=d_in; end if; end process; q<=a when enable=’1’; -- VHDL-93 If a variable is read before it is written in a process: process(enable, d_in) variable var_a: integer; begin var_a:=var_a+1; end if; end process;

35. joal 2006 HT:1 Em3 Digital Electronics Design 35 Concurrent and sequential processing Concurrent VHDL constructions process statement when-else statement with-select statement signal declaration block statement Sequential VHDL constructions if-then-else statement case statement loop statement variable declaration variable assignment return statement null statement wait statement Both concurrent and sequential signal assignment declarations of types and constants function and procedure calls assert statement after delay signal attributes

36. joal 2006 HT:1 Em3 Digital Electronics Design 36 Assert command The assert command is used to test functions and time constraints inside a VHDL model and send messages to the user ( of the simulator). Syntax: assert report severity assert in_a=’1’ or a=’0’ report ”illegal value of a” severity error An assert message is sent if the condition is not met Severity levels: note warning error failure

37. joal 2006 HT:1 Em3 Digital Electronics Design 37 Sequential VHDL. Example 1 Design a J-K-Flip-Flop with asynchronous set and reset. S R QJ K C

38. joal 2006 HT:1 Em3 Digital Electronics Design 38 Sequential VHDL. Example 2 Design an edge detector with input s, clk and reset. The detector shall generate a pulse (length=one clk pulse) on rising edge of s. QS clk