1. 1 MIPS תיאור מפושט של מעבד החיבורים המתוארים תומכים בכל שלבי פקודות R-type ו- I-type אנו נתמוך בפקודות: add, sub, or, xor, and, slt, lw, sw, beq, j כמובן שנצטרך לדעת כיצד מוסיפים פקודות נוספות כמו למשל: bne, addi, jal, jr

2. 2 עוד שלושה שבועות

3. 3 שלבי ביצוע הוראת מכונה (1) FETCH = קרא הוראה מהזיכרון ע " פ הכתובת שמכיל ה -PC. (2) DECODE = פענח את הפקודה וקרא את האוגרים הנחוצים ( אחד או שניים ). (3) EXECUTE = בעזרת ה -ALU חשב את התוצאה, או כתובת רצויה. (4) MEMORY = השתמש בתוצאה לבצע במידת הצורך : או טעינה לזיכרון (Store) או קריאה מהזיכרון (Load). (5) WRITE BACK = בצע במידת הצורך טעינה לאוגר.

4. 4 במשך כל מחזור השעון קוראים בסוף השעון כותבים cycle time rising edge falling edge קווי הבקרה - מיוצרים על פי השעון, כל עליית שעון תשנה בעקבותיה את קווי הבקרה (אם נדרש)

5. 5 Single cycle data paths Processor uses synchronous logic design (a “clock”). fT 1 MHz 1 μ s 10 MHz100 ns 100 MHz10 ns 1 GHz1 ns All state elements act like positive edge- triggered flip flops. DQ clk

6. 6 Edge-Triggered D Flip Flops DQ CLK Value of D is sampled on positive clock edge. Q outputs sampled value for rest of cycle. D Q

7. 7 Single cycle data paths: Definition All instructions execute in a single cycle of the clock (positive edge to positive edge) Advantage: a great way to learn CPUs. Drawbacks: unrealistic hardware assumptions, slow clock period

8. 8 Recall: MIPS R-format instructions Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Fetch next inst from memory:012A4020 opcodersrtrdfunctshamt Decode fields to get : ADD $8 $9 $10 “Retrieve” register values: $9 $10 Add $9 to $10 Place this sum in $8 Prepare to fetch instruction that follows the ADD in the program. Syntax: ADD $8 $9 $10Semantics: $8 = $9 + $10

9. 9 Separate Read-Only Instruction Memory 32 Addr Data 32 זכרון פקודות Reads are combinational: Put a stable address on input, a short time later data appears on output. טעינת התוכנית לזכרון לא מעניננו כרגע זכרון (מטמון) נפרד לפקודות ולנתונים (Instruction Memory & Data Memory)

10. 10 שלב 1: Straight-line Instruction Fetch 32 Addr Data 32 Instr Mem Fetching straight-line MIPS instructions requires a machine that generates this timing diagram: Why +4 and not +1? Why do we increment every clock cycle? CLK Addr DataIMem[PC + 8] IMem[PC + 4] IMem[PC] PC + 8 PC + 4PC PC == Program Counter, points to next instruction.

11. Single-cycle Implementation of MIPS Our first implementation of MIPS will use a single long clock cycle for every instruction Every instruction begins on one up (or, down) clock edge and ends on the next up (or, down) clock edge This approach is not practical as it is much slower than a multicycle implementation where different instruction classes can take different numbers of cycles –in a single-cycle implementation every instruction must take the same amount of time as the slowest instruction –in a multicycle implementation this problem is avoided by allowing quicker instructions to use fewer cycles Even though the single-cycle approach is not practical it is simple and useful to understand first Note : we shall implement jump at the very end

12. 12 New Component: Register (for PC) In later examples, we will add an “enable” input: clock edge updates state only if enable is high 32 Din Clk PC Dout 32 Built out of an array of 32 flip-flops DQ clk DQ DQ Din0 Din1 Din2 Dout0 Dout1 Dout2

13. 13 New Component: A 32-bit adder (ALU) Combinational: היציאה שווה לסכום ערכי כניסה A ו-B מלפני זמן קצר (~ ננו שניה). 32 + A B A + B 32 ALUALU A B A op B op ln(#ops) ALU: כנ"ל רק למס פונקציות רבות לפי הבורר op. Zero? Sometimes, extra outputs for use by control logic...

14. 14 Design: Straight-line Instruction Fetch CLK Addr DataIMem[PC + 8] IMem[PC + 4] IMem[PC] PC + 8 PC + 4PC Clk 32 AddrData Instr Mem 32 D PC Q 32 + 0x4 +4 in hexadecimal State machine design in the service of an ISA

15. 15 Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Fetch next inst from memory:012A4020 opcodersrtrdfunctshamt Decode fields to get : ADD $8 $9 $10 “Retrieve” register values: $9 $10 Add $9 to $10 Place this sum in $8 Prepare to fetch instruction that follows the ADD in the program. Syntax: ADD $8 $9 $10Semantics: $8 = $9 + $10 Goal #1: An R-format single-cycle CPU Done! To continue, we need registers...

16. 16 Register files: R1 R2... R31 Why is R0 special? Q Q Q R0 - The constant 0Q clk.... 32 MUXMUX sel(rs1) 5... rd1 32 MUXMUX sel(rs2) 5... rd2 “two read ports” wd D D D En DEMUXDEMUX... sel(ws) 5 WE 32

17. 17 Register File Schematic Symbol 32 rd1 RegFile 32 rd2 WE 32 wd 5 rs1 5 rs2 5 ws Why do we need WE (Write Enable)? If we had a register file w/o WE, how could we work around it?

18. Datapath: Instruction Store/Fetch & PC Increment Three elements used to store and fetch instructions and increment the PC Datapath

19. Animating the Datapath Instruction <- MEM[PC] PC <- PC + 4

20. Datapath: R-Type Instruction Two elements used to implement R-type instructions Datapath

21. Animating the Datapath add rd, rs, rt R[rd] <- R[rs] + R[rt];

22. Datapath: Load/Store Instruction Two additional elements used To implement load/stores Datapath

23. Animating the Datapath lw rt, offset(rs) R[rt] <- MEM[R[rs] + s_extend(offset)];

24. Animating the Datapath sw rt, offset(rs) MEM[R[rs] + sign_extend(offset)] <- R[rt]

25. Datapath: Branch Instruction Datapath No shift hardware required: simply connect wires from input to output, each shifted left 2 bits

26. Animating the Datapath beq rs, rt, offset if (R[rs] == R[rt]) then PC <- PC+4 + s_extend(offset<<2)

27. MIPS Datapath I: Single-Cycle Input is either register (R-type) or sign-extended lower half of instruction (load/store) Combining the datapaths for R-type instructions and load/stores using two multiplexors Data is either from ALU (R-type) or memory (load)

28. Animating the Datapath: R-type Instruction add rd,rs,rt

29. Animating the Datapath: Load Instruction lw rt,offset(rs)

30. Animating the Datapath: Store Instruction sw rt,offset(rs)

31. MIPS Datapath II: Single-Cycle Adding instruction fetch Separate instruction memory as instruction and data read occur in the same clock cycle Separate adder as ALU operations and PC increment occur in the same clock cycle

32. MIPS Datapath III: Single-Cycle Adding branch capability and another multiplexor Instruction address is either PC+4 or branch target address Extra adder needed as both adders operate in each cycle New multiplexor Important note: in a single-cycle implementation data cannot be stored during an instruction – it only moves through combinational logic Question: is the MemRead signal really needed?! Think of RegWrite…!

33. Datapath Executing add add rd, rs, rt

34. Datapath Executing lw lw rt,offset(rs)

35. Datapath Executing sw sw rt,offset(rs)

36. Datapath Executing beq beq r1,r2,offset

37. 37 Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Fetch next inst from memory:012A4020 opcodersrtrdfunctshamt Decode fields to get : ADD $8 $9 $10 “Retrieve” register values: $9 $10 Add $9 to $10 Place this sum in $8 Prepare to fetch instruction that follows the ADD in the program. Syntax: ADD $8 $9 $10Semantics: $8 = $9 + $10 Goal #1: An R-format single-cycle CPU What do we do with these?

38. 38 Computing engine of the R-format CPU 32 rd1 RegFile 32 rd2 WE 32 wd 5 rs1 5 rs2 5 ws 32 ALUALU op opcodersrtrdfunctshamt Decode fields to get : ADD $8 $9 $10 Logic What do we do with WE?

39. 39 Putting it all together... 32 rd1 RegFile 32 rd2 WE 32 wd 5 rs1 5 rs2 5 ws 32 ALUALU op Logic Is it safe to use same clock for PC and RegFile? 32 AddrData Instr Mem 32 D PC Q 32 + 0x4 To rs1, rs2, ws, op decode logic...

40. 40 Reminder: How data flows after posedge 32 rd1 RegFile 32 rd2 WE 32 wd 5 rs1 5 rs2 5 ws 32 ALUALU op Logic AddrData Instr Mem D PC Q + 0x4

41. 41 Next posedge: Update state and repeat 32 rd1 RegFile 32 rd2 WE 32 wd 5 rs1 5 rs2 5 ws D PC Q

42. 42 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Instruction Memory PC Adde r 4 ck 6 [31:26] 6 [5:0]= funct איך זה נראה בספר?

43. 43 יחידת הרגיסטרים. יחידה זו דרושה לשלב ה-decode (ולשלב ה-write back) Read register 1 Registers Read register 2 Write register Write Data Read data1 Read data2 מספרי האוגרים Data

44. 44 Arithmetic Logic operation Read register1 Registers Read register2 Write register Write Data Read data1 Read data2 ALU Zero ALU operation ALU result Instruction ALU result ALU operation הפעולה הבסיסית שנדגים הנה פקודת R-type

45. 45 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] 6 [5:0]= funct איך זה נראה בספר?

46. 46 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] 6 [5:0]= funct איך זה נראה בספר?

47. 47 The internal structure of the Register File 32 Read data 2 write data Read data 1 5 5 5 Rd reg 2 (= Rt) Rd reg 1 (= Rs) RegWrite Wr reg (= Rd) 32 E קוראים משתי היציאות בוזמנית ערכים של שני רגיסטרים שונים כותבים לאחד הרגיסטרים האחרים (בעליית השעון הבאה)

48. 48 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite

49. 49 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU ck

50. 50 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCPC ALU ck 4

51. 51 A CPU capable of R-type instructions only 5 [25:21]=Rs 5 [20:16]=Rt 5 [15:11]=Rd Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 6 [5:0]=funct ALU control

52. 52 יעד מס 2: I-format ALU instructions Syntax: ORI $8 $9 64Semantics: $8 = $9 | 64 16-bit immediate extended to 32 bits.In this example, $8 (the result register) is rt !!! (was rd previously). Zero-extend: 0x8000 ⇨ 0x00008000 Sign-extend: 0x8000 ⇨ 0xFFFF8000 Some MIPS instructions zero-extend immediate field, other instructions sign- extend.

53. 53 Computing engine of the I-format CPU 32 rd1 RegFile 32 rd2 WE 32 wd 5 rs1 5 rs2 5 ws 32 ALUALU op Decode fields to get : ORI $8 $9 64 Logic In a Verilog implementation, what should we do with rs2? 32 Ext

54. 54 Merging data paths... I-format R-format “two read ports” Add muxes How many ? Where ?

55. 55 The merged data path... 32 rd1 RegFile 32 rd2 WE 32 wd 5 rs1 5 rs2 5 ws 32 ALUALU op opcodersrtrdfunctshamt ALUsrc Ext ExtOp ALUctr RegDest

56. 56 Load,Store בניית פעולות Read address Data memory Write address Write data Read data Write Read כאן נדרש זיכרון ל- data ממנו נקרא ואליו נכתוב כמו כן יש לבצע sign extension של ה- imm שהוא רק 16bit

57. 57 Loads, Stores, and Data Memory... 32 Dout Data Memory WE 32 Din 32 Addr Syntax: LW $1, 32($2)Syntax: SW $3, 12($4) Action: $1 = M[$2 + 32]Action: M[$4 + 12] = $3 Zero-extend or sign-extend immediate field? Writes are clocked: If WE is high, memory Addr captures Din on positive edge of clock. Reads are combinational: Put a stable address on Addr, a short time later Dout is ready Note: Not a realistic main memory (DRAM) model...

58. 58 איפה ה- CPU? CPU Instruction Memory Data Memory PC

59. 59 A CPU capable of lw instructions only 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite=1 16 [15:0] 5 add Sext 16->32 Data Memory Address D. Out

60. 60 A CPU capable of lw instructions only 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite=1 16 [15:0] 5 add Sext 16->32 Data Memory Address D. Out

61. 61 A CPU capable of lw & sw instructions only 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite=0 16 [15:0] 5 add Sext 16->32 Data Memory D.In Address MeWrite=1

62. 62 A CPU capable of R-type & lw instructions (principle) 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 16 [15:0] 5 add Sext 16->32 Data Memory 5 [25:21]=Rs 6 [5:0]=funct ALU control 5 [15:11]=Rd Address

63. 63 A CPU capable of R-type & lw instructions 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 16 [15:0] 5 add Sext 16->32 Data Memory 5 [25:21]=Rs 6 [5:0]=funct ALU control Rd Address D. Out

64. 64 A CPU capable of R-type & lw/sw instructions 5 [25:21]=Rs 5 [20:16]=Rt Reg File Instruction Memory PCALU Adde r 4 ck 6 [31:26] RegWrite 16 [15:0] 5 add Sext 16->32 Data Memory 5 [25:21]=Rs 6 [5:0]=funct ALU control Rd Address D.In D. Out MemWrite

65. 65 Conditional Branches in MIPS... Syntax: BEQ $1, $2, 12 Action: If ($1 != $2), PC = PC + 4 Zero-extend or sign-extend immediate field? Action: If ($1 == $2), PC = PC + 4 + 48 Immediate field codes # words, not # bytes. Why is this encoding a good idea?

66. 66 :Branch אלמנטים דרושים להוספת ALU Zero Read register1 Registers Read register2 Write register Write Data Read data1 Read data2 Instruction Adder Sum Shift left2 Sigh Extend Branch Target מועבר ליחידת הבקרה כתוצאה הלוגית של ההשוואה 1632 PC+4 משלב ה- Fetch In addresses, we always shift left by two bits

67. 67 Design: Instruction Fetch with Branch Clk 32 AddrData Instr Mem 32 D PC Q 32 + 0x4 Syntax: BEQ $1, $2, 12 Action: If ($1 != $2), PC = PC + 4 Action: If ($1 == $2), PC = PC + 4 + 48 PCSrc 32 + Ex te nd

68. 68 שילוב כל הפקודות Read register1 Registers Read register2 Write register Write Data Read data1 Read data2 Zero ALU result Data Sign extend 32 Read address memory Write address Write data Read data Write Read 16 Add 4 PC M u x Read address Instruction memory ADD ALU result Shift left2 M u x M u x

69. 69 What is single cycle control? 32 rd1 RegFile 32 rd2 WE 32 wd 5 rs1 5 rs2 5 ws Ext RegDest ALUsrc ExtOp ALUctr MemToReg MemWr Equal RegWr 32 AddrData Instr Mem Equal RegDest RegWr ExtOp ALUsrc MemWr MemToReg PCSrc Combinational Logic (Only Gates, No Flip Flops) Just specify logic functions!

70. 70 קווי בקרה PC Instruction memory Read address Instruction 16 32 Add M u x Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 4 M u x ALU operation 3 RegWrite MemRead MemWrite PCSrc ALUSrc MemtoReg ALU result Zero ALU Data memory Address Write data Read data M u x Sign extend Add ALU result Shift left 2

71. 71 Control PC Instruction memory Read address Instruction [31–0] Instruction [20–16] Instruction [25–21] Add Instruction [5–0] MemtoReg ALUOp MemWrite RegWrite MemRead Branch R register 2 Sign extend Shift left 2 M u x 1 ALU result Zero Data memory Write data Rea d dat a M u x 1 Instruction [15–11] ALU control ALU Address

72. 72 Control

73. 73 ALU control ALU control output 000 AND 001OR 010add 110subtract 111set-on-less-than (sign of rs-rt -> rd) 00 = lw, sw 01 = beq, 10 = arithmetic ALUop

74. 74 פקודת ה- jump 4 bits 26 bits 2 bits 00 : כתובת קפיצה במילים : כתובת קפיצה בבתים 0110 101 … 101111011 00 101 … 1011110110110: הקפיצה הסופית : תוספת 4 ביטים אחרונים פירוש הפקודה: J 101 … 101111011 הפקודה הבאה נמצאת בכתובת 111111011…1001

75. 75 Jump Shift left 2 PC Instruction memory Read address Instruction [31–0] Data memory Read data Write data Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction [15–11] Instruction [20–16] Instruction [25–21] Add ALU result Zero Instruction [5–0] MemtoReg ALUOp MemWrite RegWrite MemRead Branch Jump RegDst ALUSrc I sult M u x 0 10 ALU Shift left 2 2628 Address