1. Tightly coupled INS/GPS system using particle filter D0928- system architecture and math functions Part B - Final presentation Students: Royzman Danny Peleg Nati Supervisor: Fiksman Evgeni

2. Agenda Controllers Background ▫Main controllers ▫Local controllers Infrastructure – Controllers ▫Review ▫General results display ▫G.P.S Phase 2 ÷ Phase 5 R&D Difficulties

3. Controllers Background controllers – modus operandi: The system has two modes of operation. I.N.S mode G.P.S mode In order to achieve the system goals in efficient way, the operation modes were divided into ten different phases. One I.N.S Phase Nine G.P.S Phases

4. Controllers Background Main controllers - modus operandi : The system implements 4 main controllers. Main controller1 passes commands to Main controller2. Main controller2 passes commands to Main controller3 and so on. Every Main controller returns acknowledge. Every Main controller passes commands to his local controller.

5. Controllers Background Main controllers – Main controller1: Main controller1 is the main controller of the system. Main controller1 triggers (by counting) the required system mode by implementing a sequencer block. sequencer

6. Controllers Background Main controllers - modus operandi : The data and commands are send through master\slave transceivers.

7. Controllers Background Local controllers – modus operandi: The system implements 4 local controllers.

8. Controllers Background Local controllers - modus operandi : Each Local controller controls the relevant logic.

9. Infrastructure - Controllers Events – general revision

10. Infrastructure - Controllers Events – timing chart revision

11. Infrastructure - Controllers I.N.S Phase – revision

12. Infrastructure - Controllers G.P.S Phase1 – revision

13. Infrastructure - Controllers Results display Full system operation presented in the GUI developed for the project. Thanks to the insight advised by the lab staff during part1 presentation, the results are displayed in signal tap.

14. Infrastructure - Controllers G.P.S Phase2 – block scheme

15. Infrastructure - Controllers G.P.S Phase2 – IC1

16. Infrastructure - Controllers G.P.S Phase2 – Local controller1 State Machine Diagram

17. Infrastructure - Controllers G.P.S Phase2 – IC1 Signal Tap

18. Infrastructure - Controllers G.P.S Phase2 – IC2

19. Infrastructure - Controllers G.P.S Phase2 – Local controller2 State Machine Diagram

20. Infrastructure - Controllers G.P.S Phase2 – Local controller2 Signal Tap

21. Infrastructure - Controllers G.P.S Phase3 – block scheme

22. Infrastructure - Controllers G.P.S Phase3 – Data flow In order to demonstrate data flow hardware alternation is needed: 1.Data supplier inside GPS Neff block 2.C.L in frame2

23. Infrastructure - Controllers G.P.S Phase3 – Data supplier inside GPS Neff block

24. Infrastructure - Controllers G.P.S Phase3 – Combinational Logic in frame2

25. Infrastructure - Controllers G.P.S Phase3 – IC1

26. Infrastructure - Controllers G.P.S Phase3 – Local controller1 State Machine Diagram

27. Infrastructure - Controllers G.P.S Phase3 – IC1 Signal Tap

28. Infrastructure - Controllers G.P.S Phase3 – IC2

29. Infrastructure - Controllers G.P.S Phase3 – Local controller2 State Machine Diagram

30. Infrastructure - Controllers G.P.S Phase3 – IC2 Signal Tap

31. Infrastructure - Controllers G.P.S Phase3 – IC3

32. Infrastructure - Controllers G.P.S Phase3 – Local controller3 State Machine Diagram

33. Infrastructure - Controllers G.P.S Phase3 – IC3 Signal Tap

34. Infrastructure - Controllers G.P.S Phase4 – block scheme

35. Infrastructure - Controllers G.P.S Phase4 – Data flow In order to demonstrate data flow hardware alternation is needed: Data supplier in frame1

36. Infrastructure - Controllers G.P.S Phase3 – Data supplier in frame1

37. Infrastructure - Controllers G.P.S Phase4 – IC1

38. Infrastructure - Controllers G.P.S Phase4 – Local controller1 State Machine Diagram

39. Infrastructure - Controllers G.P.S Phase4 – IC1 Signal Tap

40. Infrastructure - Controllers G.P.S Phase4 – IC2

41. Infrastructure - Controllers G.P.S Phase4 – Local controller2 State Machine Diagram

42. Infrastructure - Controllers G.P.S Phase4 – IC2 Signal Tap

43. Infrastructure - Controllers G.P.S Phase4 – IC3

44. Infrastructure - Controllers G.P.S Phase4 – Local controller3 State Machine Diagram

45. Infrastructure - Controllers G.P.S Phase4 – IC3 Signal Tap

46. Infrastructure - Controllers G.P.S Phase5 – block scheme

47. Infrastructure - Controllers G.P.S Phase5 – IC1

48. Infrastructure - Controllers G.P.S Phase5 – Local controller1 State Machine Diagram

49. Infrastructure - Controllers G.P.S Phase5 – IC1 Signal Tap

50. Infrastructure - Controllers G.P.S Phase5 – IC2

51. Infrastructure - Controllers G.P.S Phase5 – Local controller2 State Machine Diagram

52. Infrastructure - Controllers G.P.S Phase5 – IC2 Signal Tap

53. Infrastructure - Controllers G.P.S Phase5 – IC3

54. Infrastructure - Controllers G.P.S Phase5 – Local controller3 State Machine Diagram

55. Infrastructure - Controllers G.P.S Phase5 – IC3 Signal Tap

56. Infrastructure - Controllers G.P.S Phase5 – IC4

57. Infrastructure - Controllers G.P.S Phase5 – Local controller4 State Machine Diagram

58. Infrastructure - Controllers G.P.S Phase5 – IC4 Signal Tap

59. R&D Difficulties Long compilation time – we reduced the compilation needed by using signal tap. Great system complexity results in long R&D period.

60. Q&A

61. Backup