1. 1 Modeling and Optimization of VLSI Interconnect 049031 Lecture 2: Interconnect Delay Modeling Avinoam Kolodny Konstantin Moiseev

2. 2 2 Interconnect Resistance Skin depth l h w

3. 3 Effect of barrier metal on R  Copper requires sidewalls (“diffusion barriers”) around it to protect the silicon from penetration of Cu atoms Without barrier: With barrier (t b : barrier thickness) H L: line length W

4. 4 Effective resistivity is not constant: Metal resistivity is worse after scaling!

5. 5 14/03/2016 21:32VLSI_INTCourse\VI02\VI02_025 Interconnect Capacitance w l C a = ε 0 ε r t d w C x h l h C x = ε 0 ε r d C a t ε 0 = 8.85 x 10 -12 F/m; ε r = 3.9 (SiO 2 )

6. 6 Fringing Capacitance Conductor Fringing Fields  H w +

7. 7 Fringing field adds capacitance Source: Bakoglu 89

8. 8 Numerical Approximations for Capacitance Source: Shyh-Chyi Wong, Gwo-Yann Lee, and Dye-Jyun Ma, “Modeling of Interconnect Capacitance, Delay, and Crosstalk in VLSI”, IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 13, NO. 1, FEBRUARY 2000

9. 9 Accurate Capacitance Modeling * F. Stellari and A.L. Lacaita, IEEE Transactions on Electron Devices, vol.47, no,1, January 2000. Source: Shyh-Chyi Wong, Gwo-Yann Lee, and Dye-Jyun Ma, “Modeling of Interconnect Capacitance, Delay, and Crosstalk in VLSI”, IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 13, NO. 1, FEBRUARY 2000

10. 10 Accurate Cross-Capacitance Modeling * Sundaresan et al., HPCA 2005

11. 11 Simplified Capacitance Model

12. 12 Interconnect time constant

13. 13 What about the speed of light?  Assume S=W, fixed wire length RLC RC W=S [u] RC model is unrealistic here!

14. 14 Wire Delay vs. Wire Length

15. 15 RLC delay model Approximation  Inductive effects:  Longer delay  Steeper slope  overshoot RC delay RLC delay * Eby G. Friedman, Yehea E. Ismail, On- chip inductance in high speed integrated circuits, 2001 L,C and R are per unit length l denotes wire length RC model RLC model

16. 16 Fast wires must use transmission line layout  Ground plane and/or wires provide current return path w tg GROUND wg t h SS ws t wg tg GROUND h SS d h wg w SIGNAL GROUND t tg h wg w SIGNAL GROUND t tg ws t d

17. 17 Most wires don’t need inductive modeling

18. 18 Complete delay vs. wirelength Small driverLarge driver

19. 19 Rough guidelines about Inductance  Most wires operate at the RC region  Most wires are laid out at higher density, and operate slowly  RLC model is necessary only for a few wires  When propagation speed is important  Make them wide and thick to reduce R  Use Transmission line structures

20. 20 Evolution of Interconnect Models  Mode of a wire segment between two gates:  1) “Ideal” Interconnect (R=0, C=0, L=0)  2) Capacitive interconnect (C  0)  3) Resistive interconect (C  0, R  0)  4) Inductive interconnect (R  0, C  0, L  0) Technology Evolution C int R int C int R int

21. 21 Interconnect Tree: The Typical Structure Driver Receivers

22. 22 The modeling tradeoff  Accuracy  Complexity

23. 23 Circuit simulation vs. Timing Analysis

24. 24 Waveform abstraction for timing analysis Source: “Timing”, S. Sapatnekar 2004

25. 25 Response of Single RC to a Step Voltage R V out (t)V in (t) C 1 0.5 0.63 1/RC RC h(t) g(t) V out 0.69RC t

26. 26 Distributed RC line

27. 27 Transition degradation along a wire Step response of a distributed RC wire as function of location along wire and time

28. 28 Lumped vs. Distributed RC Line

29. 29 Lumped vs. Distributed RC Output potential range Time Elapsed Distributed RC Network Lumped RC Network 0 to 90% 1.0 RC 2.3 RC 10% to 90% (rise time) 0.9 RC 2.2 RC 0 to 63% 0.5 RC 1.0 RC 0 to 50% 0.4 RC 0.7 RC 0 to 10% 0.1 RC 0.1 RC מקור: Bakoglu

30. 30 What are we trying to do in the general case?  Compute the 50% delay of an RC circuit driven by a voltage step Wire model H(S) V in (t)V out (t) 1 t Vout(s) = 1/s*H(s)

31. 31 The two simple cases we know 2) Distributed RC 1) Lumped RC Why is it difficult in other (general) cases?

32. 32 Example: Delay of 2-Stage RC R V out (t)V in (t) C R C Elmore delay

33. 33 Elmore Delay: An informal introduction  Circuits with multiple RC segments are linear systems  Their transfer functions have multiple poles  Elmore delay is an approximation for the dominant pole  It is easy to calculate  We’ll define it and use it now without proof  A formal derivation will be presented later * Elmore, W. C. "The transient response of damped linear networks with particular regard to wideband amplifiers." Journal of applied physics 19.1 (1948): 55-63.‏

34. 34 Elmore delay expressions for RC tree L k is the total downstream capacitive load driven by R k R ki is the total upsteam resistance common to node k and to node i Upstream formula: Downstream formula:

35. 35 RC tree – upstream resistances driver output

36. 36 Let’s try Elmore’s formulas on wire models: V in (t) C/2 V in (t) R R/2 C/2 C/3 R/2 C/3

37. 37 Let’s try it with n segments: V in (t) R/n C/(n+1)

38. 38 RC tree: Examples of upstream resistance IN (ROOT) 0 6 4 3 2 1 C1C1 C4C4 C3C3 C2C2 C6C6 R4R4 R6R6 R3R3 R2R2 R1R1 R 32 R 22

39. 39 Examples of Elmore delay calculation

40. 40 Algorithm to compute Elmore delay in a tree

41. 41 Elmore delay as upper bound of 50% delay

42. 42 Advantages/Disadvantages of Elmore Delay  Upper bound  Easy to calulate ( 2 tree traversals)  Has high fidelity (as opposed to accuracy) + -  Pessimistic (upper bound)  Assumes ideal step input (no input slope effect)  Does not model resistive shielding

43. 43 Resistive Shielding Let’s ignore the resistive shielding effect for now

44. 44 Modeling the CMOS Driver v in (t) t d 1 v in 0.9 0.5 t t 0.1 v out t driver interconnect load For a simple capacitive load (assume ideal interconnect): Voltage at the driving point Voltage at the load

45. 45 Driver’s effective resistance

46. 46 Simple Lumped Stage Model

47. 47 R d v in v out C g R d C d C L Switch-level RC Model R Dup R Ddown

48. 48 Improved Switch level models for purely capacitive load

49. 49 Stage / gate / wire delay? Stage delay CANNOT be decomposed to gate delay + wire delay!

50. 50 A second look at the bottom of deep submicron  How to separate gate delay from wire delay?  How strong should the driving gate be? Conclusion: 50K-100K gate blocks are OK for traditional design flow.

51. 51 Summary