1. VC707 Evaluation Kit Xilinx Virtex-7 In_0 GTX 0 @320 MHz IDELAY 8B/10B Serilizer 7 0 7IDELAY 0=>K28.5 0=>K28.1 D(15:0) K(1:0) 8B/10B IDELAYCTRL LHC_Clk Clk0_M2C_P/N PLL 200 MHz Ref 6.4 Gbps 40 MHz SM Training UART (opencores 16550) J21 USB CP2103 HPC FMC (J35, LVDS pairs routed: 34, two clk_M2C pairs, one GBTCLK) NIM To LVDS In_0 In_15 In_16 In_31 In_0 In_15 NIM To LVDS Trained Error Ref 320 MHz Power Supply 12V +5V-5V HPC FMC (J64) QSFP+ 4x TX 4xRX 4x TX 4xRX @320 MHz Global Clock A10/B10 ISERDES GTX 0IDELAY 8B/10B Serilizer 7 0 7IDELAY 0=>K28.5 0=>K28.1 D(15:0) K(1:0) 8B/10B Ref ISERDES Clk 6.4 Gbps LVDS to NIM Out_0 Out_7 114.285 MHz 40.08 MHz 40.08 160.32/ 320.64 si5324 I2C Test pattern generator MuCTPiToTopo control FMC (Newer Technology) FMC with LEMO connectors (32 inputs, 8 outputs, 1 clock input and jitter cleaner)

2. FMC board with LEMO connectors goes here FMC board with 2 QSFP+ transceivers goes here USB i/f to UART: -> control USB JTAG i/f -> loading of firmware VC707 Evaluation Kit Xilinx Virtex-7 FPGA

3. Board with 2 QSFP+ transceivers Newer Technology FM-S28 http://www.fastertechnology.com/ products/fmc/fm-s28.html Board with LEMO connectors: Design, including PCB layout, almost complete Jitter cleaner still requires some work Components ordered for 5 boards, LEMO connectors for 3 boards Transceivers on other side for installed board

4. Firmware development about to be started. Expect to be ready for testing at CERN in the autumn Two VC707s to be purchased. One is to be used in initial tests as test generator and for receiving output generated by the board with the MuCTPiToTopo functionality The two VC707s will allow to construct two identical MuCTPiToTopo boxes (rack mountable pizza-boxes with provision for vertical air flow), so that there is a spare, while the second box also can be used for further firmware development if required NB: No processor in FPGA, control via UART: 8 bit characters provide enough flexibility for control of training and of normal running Monitoring functionality to be looked at QSFP+ transceivers compatible with miniPODs of L1 Topo processor, but optical budget to be checked 8 optical links, 2 needed for bandwidth, but 4-fold replication may be required

5. In_0 GTX IDELAY In_15 @320 MHz IDELAY 1st 320 MHz Clock Tick 16/20 bits @320 MHz K28.5 =0x00? 8B/10B 6.4 Gbps Replacement of 0x00 into / Solves 8-bit word alignment. Both contain Comma. Need to solve MSB/LSB alignment at Topo (usually done by ordered set Or but we choose ) or 2nd? 320 MHz Clock Tick 1620 Serializer 3rd 320 MHz Clock Tick Latency: K28.1 =0x00? Technical detail MuCTPiToTopo