1. Winter-Spring 2001Codesign of Embedded Systems1 Processes in SystemC: Examples and Exercises Part of HW/SW Codesign of Embedded Systems Course (CE 40-226)

2. Winter-Spring 2001Codesign of Embedded Systems2 Today programme Example on structural design Ripple Counter Example on Explicit state machine 101 Sequence Detector Example on Implicit state machine The same Sequence Detector Your in-class exercises Quiz!

3. Winter-Spring 2001Codesign of Embedded Systems3 Structural Design Example: Ripple Counter TFF TQ TQ TQ VCC

4. Winter-Spring 2001Codesign of Embedded Systems4 Ripple Counter (cont’d) #ifndef __TFF_H__ #define __TFF_H__ #include SC_MODULE(tff) { sc_in t; sc_in clk; sc_out q; bool val; void toggle() { if (t==true) val = !val; q = val; } SC_CTOR(tff) { SC_METHOD(toggle); sensitive_neg(clk); val = false; } }; #endif TFF

5. Winter-Spring 2001Codesign of Embedded Systems5 Ripple Counter (cont’d)... SC_MODULE(rc) { sc_in clk;sc_out q[CNTR_WIDTH]; tff *ff[CNTR_WIDTH];sc_signal vcc; SC_CTOR(rc) { char name[10]; vcc = true; ff[0] = new tff( "Bit0"); (*ff[0])<< vcc<< clk<< q[0]; for(int i=1; i<CNTR_WIDTH; i++) { ff[i] = new tff( itoa(i, name, 10)); (*ff[i])<< vcc<< q[i-1]<< q[i]; } }; TFF

6. Winter-Spring 2001Codesign of Embedded Systems6 SystemC_Win output

7. Winter-Spring 2001Codesign of Embedded Systems7 Explicit State-Machine: 101 Sequence Detector Start S1 1 S10 0 S101 1 0 0 10 1

8. Winter-Spring 2001Codesign of Embedded Systems8 101 Seq. Det. (cont’d) StartS1 1 S10 0 S101 1 0 0 10 1 enum states { START, S1, S10, S101 }; SC_MODULE(seq_det) { sc_in_clk clk; sc_in s; sc_out z; states current_state, next_state; void change_state() { z = false; switch(current_state) { case START: if (s==true) next_state = S1; else next_state = START; break; case S1:... case S10:... case S101: z = 1; if (s==(bool)1) next_state = S1; else next_state = S10; } current_state = next_state; }... }

9. Winter-Spring 2001Codesign of Embedded Systems9 SystemC_Win output

10. Winter-Spring 2001Codesign of Embedded Systems10 101 Seq. Det.: IMPLICIT state-machine void change_state_thread() { while (true) { z = 0; while (s==(bool)0) wait(); // 1 is detected up to now do wait(); while (s==(bool)1); // 10 is detected up to now do wait(); while (s==false); // The complete sequence (101) is detected now z = 1; wait(); }}

11. Winter-Spring 2001Codesign of Embedded Systems11 101 Seq. Det.: IMPLICIT state-mach. (cont’d) SC_CTOR(seq_det) { /*SC_THREAD(change_state_thread); sensitive_pos<<clk; */ SC_CTHREAD(change_state_thread, clk.pos()); } Changes required in SC_MODULE constructor:

12. Winter-Spring 2001Codesign of Embedded Systems12 SystemC_Win output

13. Winter-Spring 2001Codesign of Embedded Systems13 Your in-class exercises: Hierarchical design (cont’d) DFF Register RShift Reg Gates Single bit Full Adder Serial Adder RShift Reg + parallel load Shift Reg shl/shr input Barrel Shifter N-bit Adder Array Multiplier One Stage of Pipelined Multiplier Pipelined Multiplier

14. Winter-Spring 2001Codesign of Embedded Systems14 Complementary notes: Extra classes “VHDL Short Course” by A.M. Ghare-Baghi First session date-time: Monday, Ordibehes 10th, 18 O’clock Place: Kwarizmi Hall, CE Dept. “HW Synthesis Techniques Seminar” by S. Safari Date-Time: Saturday, Ordibehesht 8th, 13 O’clock Place: Kwarizmi Hall, CE Dept.

15. Winter-Spring 2001Codesign of Embedded Systems15 Second Quiz Design a ?