1. Digital System Design Verilog ® HDL Dataflow Modeling Maziar Goudarzi

2. Objectives of this Topic The assign statement Expressions, operators, and operands Issues with 4-valued logic Specifying delays in Dataflow modeling 2010DSD2

3. Introduction Usages of gate-level modeling – Small designs – Netlist of gates, Logic Synthesis Next level up: Dataflow modeling – Continuous assignment The assign keyword module my_and(output out, input in1, in2); assign out = in1 & in2; endmodule 2010DSD3

4. Rules for assign statement LHS data type: only net ( wire ) RHS data type: any type (register, net) or function 2010DSD4

5. Implicit continuous assignment 2010DSD5 Implicit net declaration

6. Gate Level vs. Dataflow Modeling module mux4_to_1 (output out, input i0, i1, i2, i3, s1, s0); wire s1n, s0n, y0, y1, y2, y3; not (s1n, s1); not (s0n, s0); and (y0, i0, s1n, s0n); and (y1, i1, s1n, s0); and (y2, i2, s1, s0n); and (y3, i3, s1, s0); or (out, y0, y1, y2, y3); endmodule module mux4_to_1 (output out, input i0, i1, i2, i3, s1, s0); assign out = (~s1 & ~s0 & i0)| (~s1 & s0 & i1)| ( s1 & ~s0 & i2)| ( s1 & s0 & i3); endmodule 2010DSD6 Gate Level Model Dataflow Model

7. Another alternative for Mux 4-to-1 2010DSD7 Use conditional operator

8. 4-bit Full-adder Example 2010DSD8

9. Expression, Operand, Operator 2010DSD9 integer count, final_count; final_count = count + 1;// integer operand real a, b, c; c = a - b; // real operands reg [15:0] reg1, reg2; reg [3:0] reg_out; reg_out = reg1[3:0] ^ reg2[3:0];// part-select operands reg ret_value; ret_value = calculate_parity(A, B); // function type oprnd

10. Operators Operator categoryOperators symbol Arithmetic * / + - % ** Logical ! && || Relational > = Equality == != === !=== Bitwise ~ & | ^ ^~ ~^ Reduction & ~& | ~| ^ ~^ ^~ Shift >> >> <<< Concatenation { } Replication { { } } Conditional ? : 10

11. Arithmetic Operators 4-valued logic issue: x and z values 2010DSD11 in1 = 4'b101x; in2 = 4'b1010; sum = in1 + in2; A = 4'b0011; B = 4'b0100; D = 6; E = 4; F=2; A * B D / E A + B B - A F = E ** F; 13 % 3 16 % 4 -7 % 2 7 % -2 +5 -4 -10/5 -6’d10/5 // Do NOT use // =(2's complement of 10)/5 // =(2 32 - 10)/5

12. Logical and Relational Operators Outcome: 0,1,x ‘x’ value usually treated as false 2010DSD12

13. Equality Operators 2010DSD13 // A = 4, B = 3 // X = 4'b1010, Y = 4'b1101 A == B X != Y // Z = 4'b1xxz, M = 4'b1xxz // N = 4'b1xxx X == Z Z === M Z === N M !== N

14. Bitwise Operators // X = 4'b1010 // Y = 4'b1101 // Z = 4'b10x1 ~X X & Y X | Y X ^ Y X ^~ Y X & Z 2010DSD14 Bitwise vs. Logical operators Bit-width mismatch issue

15. Reduction Operators // X = 4'b1010 &X |X ^X 2010DSD15

16. Shift Operators // X = 4'b1100 Y = X >> 1; Y = X << 1; Y = X << 2; integer a, b, c; a = 0; b = -10; c = a + (b >>> 3); 2010DSD16

17. Concatenation Operator Unsized operands not allowed 2010DSD17 // A = 1'b1, B = 2'b00, // C = 2'b10, D = 3'b110 Y = {B, C} Y = {A, B, C, D, 3'b001} Y = {A, B[0], C[1]}

18. Replication Operator 2010DSD18 reg A; reg [1:0] B, C; reg [2:0] D; A = 1'b1; B = 2'b00; C = 2'b10; D = 3'b110; Y = { 4{A} } Y = { 4{A}, 2{B} } Y = { 4{A}, 2{B}, C }

19. Conditional Operator 2010DSD19 assign addr_bus = drive_enable ? addr_out : 36'bz; assign out = control ? in1 : in0; assign out = (A == 3) ? ( control ? x : y ): ( control ? m : n) ;

20. Operators Precedence Unary * / % + - >> << > == != === !== Reduction Logical Conditional 2010DSD20

21. Example: Carry Look ahead Adder 201021 module fulladd4(sum, c_out, a, b, c_in); output [3:0] sum; output c_out; input [3:0] a,b; input c_in; wire p0,g0, p1,g1, p2,g2, p3,g3, c4, c3, c2, c1; assign p0 = a[0] ^ b[0], p1 = a[1] ^ b[1], p2 = a[2] ^ b[2], p3 = a[3] ^ b[3]; assign g0 = a[0] & b[0], g1 = a[1] & b[1], g2 = a[2] & b[2], g3 = a[3] & b[3]; assign c1 = g0 | (p0 & c_in), c2 = g1 | (p1 & g0) | (p1 & p0 & c_in), c3 = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 & c_in), c4 = g3 | (p3 & g2) | (p3 & p2 & g1) | (p3 & p2 & p1 & g0) | (p3 & p2 & p1 & p0 & c_in); assign sum[0] = p0 ^ c_in, sum[1] = p1 ^ c1, sum[2] = p2 ^ c2, sum[3] = p3 ^ c3; assign c_out = c4; endmodule

22. Example: 4-bit Ripple Carry Counter 2010DSD22

23. Sequential Logic at Dataflow Level Negative Edge Triggered D-FF 2010DSD23 module edge_dff(q, qbar, d, clk, clear); output q,qbar; input d, clk, clear; wire s, sbar, r, rbar,cbar; assign cbar = ~clear; assign sbar = ~(rbar & s), s = ~(sbar & cbar & ~clk), r = ~(rbar & ~clk & s), rbar = ~(r & cbar & d); assign q = ~(s & qbar), qbar = ~(q & r & cbar); endmodule

24. Edge-Triggered T-FF 2010DSD24 module edge_dff(q, qbar, d, clk, clear);... endmodule module T_FF(q, clk, clear); output q; input clk, clear; edge_dff ff1(q,,~q, clk, clear); endmodule

25. Design by Truth Table 2010DSD25

26. Specifying Delays at Dataflow Level 1.Regular Assignment Delay assign #10 out = in1 & in2; 2.Implicit Continuous Assignment Delay wire #10 out = in1 & in2; //same as wire out; assign #10 out = in1 & in2; 3.Net Declaration Delay wire # 10 out; assign out = in1 & in2; 2010DSD26

27. Delays at Dataflow Level are Inertial Delay 2010DSD27 assign #10 out = in1 & in2;

28. Have you learned this topic? Syntax of the assign statement Operators and 4-valued logic issues How to specify delays in Dataflow modeling 2010DSD28