1. Evolvable Hardware (EHW) Topic Review S08*ENGG*6530 Antony Savich

2. 2A. SavichS08*ENGG*6530 - EHW Topic Review Outline Motivation Concept details Problems and bottlenecks General applications Personal Retrospect Conclusion Design project summary

3. 3A. SavichS08*ENGG*6530 - EHW References Jim Torresen, An Evolvable Hardware Tutorial. In proc. of 14th International Conference on Field Programmable Logic and Applications (FPL'2004), August 2004, Antwerp - Belgium P Haddow, G Tufte, P Van Remortel, Evolvable hardware: pumping life into dead silicon. In On Growth, Form and Computers. Sanjeev Kumar, Peter J. Bentley, Editors. Elsevier, 2003 Langdon, W.B. and Gustafson, S. (2005) Genetic Programming and Evolvable Machines: five years of reviews. Genetic Programming and Evolvable Machines, 6 (2). pp. 221-228. Springer, 2005

4. 4A. SavichS08*ENGG*6530 - EHW What is Evolvable Hardware? EHW is hardware which is generated or regenerated by special means Goal: improve circuit performance parameters via dynamic autonomous regeneration speed, area, power, output quality speed, area, power, output quality Hardware Auto Evolution

5. 5A. SavichS08*ENGG*6530 - EHW What do we normally do? Hardware engineering Application analysis Application analysis Requirement specification Requirement specification Circuit design (RTL, layout, routing) Circuit design (RTL, layout, routing) Test suite formulation Test suite formulation Circuit verification and validation Circuit verification and validationSimulationHardware Field performance evaluation Field performance evaluation

6. 6A. SavichS08*ENGG*6530 - EHW What do we normally do?

7. 7A. SavichS08*ENGG*6530 - EHW Why should we bother? From design specification on, 85% (approx) of human time is spent on product (circuit) generation 85% (approx) of human time is spent on product (circuit) generation Design complexity exponentially increases Easy to hierarchaly specify Easy to hierarchaly specify Difficult to optimize as a whole Difficult to optimize as a whole Human time = expensive Machine time = cheap…….

8. 8A. SavichS08*ENGG*6530 - EHW Why should we bother? Sizing limitation is not valid (Moore’s law) ~1billion transistors per chip (Intel 2006) ~1billion transistors per chip (Intel 2006) How much is this better than ~100million tr. chips? How much is this better than ~100million tr. chips? Designability is the current hurdle Nowadays, improvement in transistor count does not equate to a similar functional or performance improvement, the gap grows…

9. 9A. SavichS08*ENGG*6530 - EHW What is the benefit? If it were possible to evolve inefficient circuits… The circuits created by evolution can be: much simpler than human creations much simpler than human creations not always comprehendible by humans not always comprehendible by humans

10. 10A. SavichS08*ENGG*6530 - EHW By autoevolution we get… Reduced complexity, smaller circuits In turn helps simplify the evolutionary process In turn helps simplify the evolutionary process More efficient circuits Better performing circuits New ideas and innovation At the expense of machine time… gives us extra time to do other things than do boring circuit design?

11. 11A. SavichS08*ENGG*6530 - EHW How do we do it? Specification

12. 12A. SavichS08*ENGG*6530 - EHW How do we do it? Usually implies evolutionary techniques: Genetic Algorithms Genetic Algorithms Genetic Programming Genetic Programming Evolutionary Programming Evolutionary Programming

13. 13A. SavichS08*ENGG*6530 - EHW How do we do it? Can be applied to various circuits Digital (commercial or custom) Digital (commercial or custom) Analog Analog Off-line or on-line evolution

14. 14A. SavichS08*ENGG*6530 - EHW How do we do it? Random using defined representation Determine fitness Use requirements Implement on technology Evolve

15. 15A. SavichS08*ENGG*6530 - EHW How do we do it? Random using defined representation Ideas? Need to map a circuit description (phenotype) to an evolutionary technique description (genotype) How do we represent a circuit?

16. 16A. SavichS08*ENGG*6530 - EHW How FPGAs are relevant? FPGAs are a natural example of reconfigurable example of reconfigurable digital technology Can use the programming bitstream as the genotype directly Can rapidly reconfigure to fit new solutions

17. 17A. SavichS08*ENGG*6530 - EHW How do we do it? Need to evaluate generated circuits (typically many) Assign a fitness parameter How would you normally evaluate a circuit?

18. 18A. SavichS08*ENGG*6530 - EHW Evaluation methods

19. 19A. SavichS08*ENGG*6530 - EHW How do we do it? Use requirements What are the evaluation criteria for fitness?

20. 20A. SavichS08*ENGG*6530 - EHW Problem Redefinition Sometimes… The task of finding a solution is redefined as a task of Specifying the problem Specifying the problem Representing the solution Representing the solution Sometimes, one is not easier than the other

21. 21A. SavichS08*ENGG*6530 - EHW How do we do it? Evolve This step depends on the algorithm you choose, In EHW this is typically GA (genetic algorithms)

22. 22A. SavichS08*ENGG*6530 - EHW Genetic Algorithm Parents Evolution Children Initial circuit population using a chosen representation

23. 23A. SavichS08*ENGG*6530 - EHW A cycle of evolution

24. 24A. SavichS08*ENGG*6530 - EHW Issues by design… Using FPGAs leads naturally to direct mapping (genotype – phenotype) Creates a search space explosion for larger circuits Creates a search space explosion for larger circuits Indirect mapping – reduces genotype description vs. phenotype requirements Less information in genotype, not all phenotypes are mapped (best solution may be skipped) Less information in genotype, not all phenotypes are mapped (best solution may be skipped) Changes complexity of finding a best solution into complexity of finding the right mapping to include it Changes complexity of finding a best solution into complexity of finding the right mapping to include it

25. 25A. SavichS08*ENGG*6530 - EHW Issues by design… Representation of genes – quick failure If short, 1’s or 0’s, a single bit mutation may lead to complete circuit failure If short, 1’s or 0’s, a single bit mutation may lead to complete circuit failure It’s difficult to encode genes in a genotype such that a small gene change will result in small functionality change It’s difficult to encode genes in a genotype such that a small gene change will result in small functionality change

26. 26A. SavichS08*ENGG*6530 - EHW Issues by design… Technological evolution is a problem Better flexibility means increased granularity Better flexibility means increased granularity Increased complexity means larger phenotype Increased complexity means larger phenotype Larger phenotype means slower configuration times Larger phenotype means slower configuration times New heterogeneous FPGA features pose mapping difficulties – not EHW friendly. New heterogeneous FPGA features pose mapping difficulties – not EHW friendly. Complexity of system means complexity of fitness functions, longer evaluation times

27. 27A. SavichS08*ENGG*6530 - EHW Solutions ‘Virtual’ FPGAs are possible: Reduce genotype by simplifying routing choices; logic component choices Reduce genotype by simplifying routing choices; logic component choices Can be mapped onto commercial FPGAs Can be mapped onto commercial FPGAs

28. 28A. SavichS08*ENGG*6530 - EHW Solutions Development of EHW friendly features Map only the features that are suitable for evolution Map only the features that are suitable for evolution Partially evolvable systems Design most of the system (fixed portion) Design most of the system (fixed portion) Allow only a portion to be evolved Allow only a portion to be evolved

29. 29A. SavichS08*ENGG*6530 - EHW An Interesting Application On-line evolutionary systems: Create competing nodes Create competing nodes Operate one in real time Operate one in real time Evolve others in parallel Evolve others in parallel Another reaches maturity - swap Another reaches maturity - swap

30. 30A. SavichS08*ENGG*6530 - EHW Personal Retrospective: 1 On-line HW/SW evolvable system: Why only require hardware execution vs. software processing? Why only require hardware execution vs. software processing? Why only evolve hardware? Why only evolve hardware? The key – hardware/software cohabitation within an on-line self-evolvable system.

31. 31A. SavichS08*ENGG*6530 - EHW Personal Retrospective: 1 Evolving a scheduled Unit (co-evolution) Task set {1..n} Scheduled for optimization Task set {1..m} Soft model Hard model Load monitor & scheduler With current advances in self-reconfiguration technology and device size, this is all possible as a SoC!

32. 32A. SavichS08*ENGG*6530 - EHW Personal Retrospective: 2 Current research: Neural Network (ANN) implementations Rough model of the brain Rough model of the brain ANNs provide approximating solutions to problems ANNs provide approximating solutions to problems ANNs are trained on a sample of the problem space ANNs are trained on a sample of the problem space Quality of results highly depends on parameters used in constructing ANN: Topology (number and type of neurons) Topology (number and type of neurons) Arithmetic representation Arithmetic representation Learning function Learning function

33. 33A. SavichS08*ENGG*6530 - EHW Personal Retrospective: 2 Fitness determined by training a configuration Training is expensive, best done in hardware (currently FPGA), many configs to train This process can benefit from automated design evolution, the technology is directly correlated with EHW methods:

34. 34A. SavichS08*ENGG*6530 - EHW Summary: EHW Circuit Need a Represented by Phenotype 1011010101010100 Genotype 101011 Reduce- Encoded by Evolved using GA Fitness Evaluated Technology Implemented on

35. 35A. SavichS08*ENGG*6530 - EHW Topic Conclusion Evolvable Hardware – great circuits made easy (in theory) Typically Genetic Algorithm is used to evolve Rephrases the “circuit design” problem into the “pheno-genotype... mapping” problem. Currently, can evolve small circuits New hardware not friendly

36. 36A. SavichS08*ENGG*6530 - EHW Course Project Direction Take an existing architecture monolithic, full hardware acceleration monolithic, full hardware acceleration a type of ANN for this project a type of ANN for this project Use Tensilica tools Profile and map portions of hardware to produce: software execution + smaller accelerator software execution + smaller accelerator Goal: compare resulting performance vs. consumption of FPGA resources.

37. 37A. SavichS08*ENGG*6530 - EHW S. Dali, Man with His Head Full of Clouds, 1936 Thank you