1. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 1 Slide 1 Alice Bean Fermilab/University of Kansas for the D0 Run2b silicon group October 15, 2001 7th International Conference on Advanced Technology and Particle Physics Design of an Upgraded DØ Silicon Microstrip Tracker for Fermilab Run 2b

2. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 2 Slide 2 Outline u Run2b Concept u Boundary Conditions for Design u Tracker Layout u Performance u Conclusions

3. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 3 Slide 3 Run 2 Physics Goals Need two experiments operating detectors with good b-tagging efficiency to see Higgs. Each experiment needs to obtain 15 fb -1

4. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 4 Slide 4 Run 2b u Although we just built a major silicon detector and are still commissioning it, a new silicon detector is planned; major undertaking. u Current silicon detector designed for ~ 2 fb -1 u Laboratory supports extended running to ~ 15 fb -1 per experiment p Run 2a Lifetime studies by both collider experiments

5. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 5 Slide 5 Implications of Run 2b u 2a Detectors will survive 2 fb -1 with high degree of confidence u Inner Layers will definitely not survive 15 fb -1 u Detectors will require modifications to exploit full physics potential of Tevatron ä Boundary conditions set by the laboratory  Limited budget for replacement  New detectors to be designed to operate with confidence throughout Run2b with integrated luminosity of at least 15 fb -1  Installation of new detectors in single shutdown of no more than 6 months duration in the year ’04 p Option chosen by both collider collaborations is to fully replace the existing silicon detectors, without retrofitting the existing DAQ system

6. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 6 Slide 6 Boundary Condition: DAQ u Retain readout system downstream of adapter card u Cable plant allows for 912 low mass / high mass cables 3/6/8/9 Chip HDI Sensor 8’ Low Mass Cable ~19’-30’ High Mass Cable (3M/80 conductor) HV / LV Adapter Card KSU Interface Board CLKs retain p Some changes to voltage distribution will have to be made

7. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 7 Slide 7 Irradiation Studies u Studies carried out with ELMA and CDF layer 00 sensors from Hamamatsu and Micron. u Measurements agree well with other measurements Conclude that the design value for Silicon operating temperature at the inner layer should be T= -10 o C

8. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 8 Slide 8 Design Considerations u No compromise on performance compared to Run2a u Minimize the variety of different components u Modular design  Provide stand-alone tracking up to |  | < 2.0

9. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 9 Slide 9 Design Choices  Drilled Be Beampipe with ID of 0.96”, 500  m wall thickness u Employ only single sided silicon u Three different sensor types: 2, 3 and 5-chip wide u Six layers, divided in two radial groups  Inner layers: Layers 0 and 1 »Axial readout only »Mounted on integrated support »Assembled into one unit »Designed for V bias up to 1000 V  Outer layers: Layers 2-5 »Axial and stereo readout »Stave support structure »Designed for V bias up to 300 V u No element supported from the beampipe

10. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 10 Slide 10 Comparison 2a and 2b  2a: »Innermost radius 25.7 mm »Outermost radius 94.3 mm  2b: »Innermost radius 17.5 mm »Outermost radius 163.6 mm End views drawn to scale

11. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 11 Slide 11 Design Choices u Sensor lengths  Inner layers: 78.4 mm, 6 sensors per half-module  Outer layers: 100 mm, 5 or 6 sensors per half-module u Longitudinal segmentation  Readout is ganged in outer layers  Hybrids are double-ended and service two readout segments Layers 2 and 3 Layers 4 and 5 Sensors are wirebonded hybrid Two hybrids per stave 100mm long sensor

12. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 12 Slide 12 Design Choices u Si temperature of inner layer should be kept at T=-10 o C  Heat Load »~30 Watts ambient »~20 Watts at 15 fb -1 at innermost layer (T= -10 o C) »~0.5 Watts per readout chip u Cooling will use 40%-60% water/ethylene-glycol mixture  T clnt = -15 o C  Option to go to T clnt = -20 o C with second chiller for inner layers u Heat load too high to allow for readout chips to be mounted on silicon: analogue cables, off-board electronics for innermost layer Detector Hybrid Analogue cable Digital cable DØ L0 CDF layer 00 Analogue cables

13. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 13 Slide 13 Layer 0 Analog cables Silicon sensors Carbon foam structure lined with Carbon fiber Uses Peek cooling tubes Hybrids mounted off-board connected to silicon with Analog cables Hybrid out of detector volume

14. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 14 Slide 14 Layer 1 Digital cables Hybrid circuit Silicon sensor Carbon foam structure similar to that of Layer 0 Layer 1 is mounted together with Layer 0 Hybrids are mounted directly on the silicon Layer 0

15. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 15 Slide 15 Outer Layers u Staves are assembled from readout modules u There will be 6 types of readout modules:  10-10 (axial, stereo)  10-20 (axial, stereo)  20-20 (axial, stereo) u Ganged sensors will have traces aligned u Stereo angle determined by mechanical constraints  10cm readout:  = 2.5 o  20cm readout:  = 1.25 o 20-20 Stereo Module

16. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 16 Slide 16 Stave Structure u Stave is doublet structure of many readout modules  Two layers of silicon »Axial and stereo  separated by PEEK cooling lines u Staves are mounted in end carbon fiber bulkheads

17. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 17 Slide 17 Stave Readout Schematic u Hybrid  Digitizes Si analogue signal, launches the digital signal on the … u Digital Jumper cable  Flex circuit which brings signals to the … u Junction card  Passive element which transfers signals to high quality twisted pair signal cable which brings the signal to the … u Adapter card  Active element that provides the differential drive for the svx4 chip HybridsDigital CablesJunction Card Twisted Pair Layers 2 and 3

18. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 18 Slide 18 Hybrids u Characteristics:  Layer 0 »2-chip hybrids; each hybrid reads out one sensor  Layers 1-5 »Hybrids are double ended v 6-chip hybrids for layer 1 v 10-chip hybrids for layers 2-5  Made of ceramic (BeO) »Silkscreening and etching »Can have multiple layers u Hybrids carry the bias voltage for layers 2-5 (300 V)  One HV feed / hybrid;  HV is split between up to 4 sensors  HV fed through AVX 50 pin connector 6-chip hybrid

19. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 19 Slide 19 SVX4 Chip u Nov ’00 decision to employ common readout chip for CDF and DØ  SVX4 in deep sub-micron, 0.25  m technology, intrinsically rad-hard »Brand new chip with own personality/features  Commercial foundries used u Test chip submitted to MOSIS 06/04/01 (Full submission 11/01)  16 channels LBL design preamp + pipeline  48 channels FNAL design preamp + pipeline »Common bias preamp+pipeline as in SVX3 »12 different input transistor sizes used to optimize noise  ENC = 450e + 43.0e/pF (optimum) LBL Pre-amp FNAL Pre-amp Pipeline

20. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 20 Slide 20 Parameters u Comparing channel count:  2a: 792576 channels  2b: 952320 channels u Cable plant is slightly smaller

21. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 21 Slide 21 Performance  A full GEANT simulation has been done with D0 reconstruction code used to analyze the results  The occupancy as a function of radius is shown here with and without noise. For the innermost layer, the mean occupancy is around 2%

22. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 22 Slide 22 Hit resolutions for WH events Resolution for inner layers for all clusters

23. Dzero Collaboration Meeting, Sept. 14, 2001 - M. DemarteauEric Flattum - Fermilab 23 Slide 23 B-tagging and mis-tagging rates Efficiencies are found using a impact parameter significance algorithm as a function of  the efficiency is 19% higher than that for the Run2a detector at the same mistag rate

24. Conclusions u The goal of the D0 Run2b detector is to provide adequate b-tagging efficiency to help discover the Higgs with 15fb -1 of data u There were many constraints that led the design of the detector including those from time, space available, cost, and integration into the present D0 DAQ system. u A 6 layer barrel device was chosen to maximize our physics capacity u The design of the detector is proceeding on all fronts u The performance as benchmarked using a full GEANT simulation with the D0 reconstruction code shows that we will have a device superior to the Run2a silicon detector particularly for tagging b quark jets