1. Memory Organisation & Modes of Operations By: Prof. Mahendra B. Salunke Asst. Prof., Department of Computer Engg, SITS, Pune-41 Email: msalunke@gmail.com URL: microsig.webs.com

2. Contents Device Register Map Overview User Configurable Memory Map Modes of operations

3. Device Register Map Overview

4. User Configurable Memory Map

5. Detailed Register Map

14. TIM Detailed Register Map

16. TIM

17. Detailed Register Map

18. ATD Detailed Register Map

23. PWM Detailed Register Map

29. PIM Detailed Register Map

30. PIM Detailed Register Map

31. PIM Detailed Register Map

32. PIM Detailed Register Map

33. PIM Detailed Register Map

34. PIM Detailed Register Map

35. PIM Detailed Register Map

36. Modes of Operations The states of the MODC, MODB, and MODA pins during reset determines the mode of operation MODCMODBMODAMode 000Special Single Chip 001Emulation Expanded Narrow 010Special Test (Expanded Wide) 011Emulation Expanded Wide 100Normal Single Chip 101Normal Expanded Narrow 110Special Peripheral Mode 111Normal Expanded Wide

37. Modes of Operations There are two basic types of operating modes: –Normal modes: Some registers and bits are protected against accidental changes. –Special modes: Allow greater access to protected control registers and bits for special purposes such as testing. Note: Expanded modes applicable for 80pin package version.

38. Normal expanded wide mode Ports A and B are configured as a 16-bit multiplexed address and data bus and port E provides bus control and status signals. This mode allows 16-bit external memory and peripheral devices to be interfaced to the system

39. Normal expanded narrow mode Ports A and B are configured as a 16-bit address bus and port A is multiplexed with 8-bit data. Port E provides bus control and status signals. This mode allows 8-bit external memory and peripheral devices to be interfaced to the system.

40. Normal single-chip mode There is no external expansion bus in this mode. The processor program is executed from internal memory. Ports A, B, K, and most of E are available as general-purpose I/O.

41. Special single-chip mode This mode is generally used for debugging single-chip operation, boot-strapping, or security related operations. The active background mode is in control of CPU execution and BDM firmware is waiting for additional serial commands through the BKGD pin. There is no external expansion bus after reset in this mode.

42. Emulation expanded wide mode Developers use this mode for emulation systems in which the users target application is normal expanded wide mode.

43. Emulation expanded narrow mode Developers use this mode for emulation systems in which the users target application is normal expanded narrow mode.

44. Special test mode Ports A and B are configured as a 16-bit multiplexed address and data bus and port E provides bus control and status signals. In special test mode, the write protection of many control bits is lifted so that they can be thoroughly tested without needing to go through reset.

45. Special peripheral mode This mode is intended for Freescale Semiconductor factory testing of the system. The CPU is inactive and an external (tester) bus master drives address, data, and bus control signals.

46. Low Power Modes Stop mode Pseudo stop mode Wait mode

47. Stop mode Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode. Wake up from this mode can be done via reset or external interrupts.

48. Pseudo stop mode Entered by executing the CPU STOP instruction. The oscillator is still running and the real time interrupt (RTI) or watchdog (COP) sub module can stay active. Other peripherals are turned off. Consumes more current than the full stop mode, but the wake up time from this mode is significantly shorter.

49. Wait mode Entered by executing the CPU WAI instruction. In this mode the CPU will not execute instructions. The internal CPU signals (address and data bus) will be fully static. All peripherals stay active. For further power consumption reduction the peripherals can individually turn off their local clocks.

50. Contact Details: Email: msalunke@gmail.com URL: microsig.webs.com