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Reduction only needed for p+p and light A+A calibration runs Generate primitives for level 2 (Ring count in RICH) Electron trigger at low transverse momenta.

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Presentation on theme: "Reduction only needed for p+p and light A+A calibration runs Generate primitives for level 2 (Ring count in RICH) Electron trigger at low transverse momenta."— Presentation transcript:

1 Reduction only needed for p+p and light A+A calibration runs Generate primitives for level 2 (Ring count in RICH) Electron trigger at low transverse momenta -> access to rare probes: At high transverse momenta: photons, electrons from W-decay, Drell Yan electrons, charged hadrons At low transverse momenta : Electrons from heavy flavor decays Global Et? EMCal/RICH Trigger Layout Possible Triggers: Kenneth Barish 11 February, 2000

2 Current Layout AMU/ADC Module Trigger Module 256 8bit FADC words RICH Local Level 1 FEM Boards Ersatz Trigger Cards x 172 x 3 RICH EMC to GL1 NIM Logic to GL1

3 FEM Boards (input from 12x12 EMCal towers) x 172... Ersatz Trigger Card to NIM logic or Local Level 1 EMCal Front End Board and Trigger Card Input: 172 Supermodules with 12x12 towers

4 AMU/ADC Module Trigger Module 256 8bit FADC words RICH Local Level 1 FEM Boards Ersatz Trigger Cards x 172... MuId ROC x 8 (2 for each threshold) o Use MuId ROC to feed ETC output into data stream and trigger system o Place data receiver module for EMCal data and electron trigger board into RICH local level 1 board for easy access to RICH data. Are RICH primitives (Adjacency check on Tiles, Ring Sums) still required input at Level 2 or can this be generated at level 2 based on increased processing power? If yes, when will the RICH local level 1 be built? RICH EMC to GL1 RICH/EMCal Layout Option #1

5 172 EMCal Channels 256 RICH Channels East Arm West Arm FPGA’s GL-1 Possible EMCal LL1 Logic

6 RICH EMCal RICH EMCal RICH EMCal RICH EMCal RICH EMCal Possible Logic Inside FPGA’s

7 RICH/EMCal Layout Option #2 AMU/ADC Module Trigger Module New RICH/EMCal Local Level 1 FEM Boards Ersatz Trigger Cards x 172... MuId ROC x 8 (2 for each threshold) o Use MuId ROC for prompt.OR. and to transfer ETC output via Glink. o Combined RICH/EMCal local level 1 crate. Use existing design (8Rx) as data receiver cards. New Electron Trigger Board. RICH EMC x 8 (for 256 trigger tiles in 8 FE crates) to GL1 GLink

8 EMC/RICH Funding Prospects AMU/ADC Module Trigger Module New RICH/EMCal Local Level 1 FEM Boards Ersatz Trigger Cards x 172... MuId ROC x 8 (2 for each threshold) o Use MuId ROC for prompt.OR. and to transfer ETC output via Glink. o Combined RICH/EMCal local level 1 crate. Use existing design (8Rx) as data receiver cards. New Electron Trigger Board. RICH EMC x 8 (for 256 trigger tiles in 8 FE crates) to GL1 GLink (100k) (50k) UCR RBRC 160k (funds req. JFY00) US/J (JFY99/00) (FY00/01)

9 Outstanding Issues LVL-1 –EMCal Rejection power needed Number of EMCal trigger elements (possible 172) How to realize E t trigger Threshold issues –RICH Number of RICH trigger elements (possible 256) Overlapping tiles? FADC or threshold? –Rejection power needed LVL-2 –Is ring count needed from LVL1? –Electron candidates needed from LVL1. (Brian Cole) –What information needs to be in data streme from LVL1 for LVL2? Offline –What information needs to be in data streme


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