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Authors : Baohua Yang, Jeffrey Fong, Weirong Jiang, Yibo Xue, and Jun Li. Publisher : IEEE TRANSACTIONS ON COMPUTERS - 2012 Presenter : Chai-Yi Chu Date.

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Presentation on theme: "Authors : Baohua Yang, Jeffrey Fong, Weirong Jiang, Yibo Xue, and Jun Li. Publisher : IEEE TRANSACTIONS ON COMPUTERS - 2012 Presenter : Chai-Yi Chu Date."— Presentation transcript:

1 Authors : Baohua Yang, Jeffrey Fong, Weirong Jiang, Yibo Xue, and Jun Li. Publisher : IEEE TRANSACTIONS ON COMPUTERS - 2012 Presenter : Chai-Yi Chu Date : 2012/11/14 1

2  Introduction  Related Work  Algorithm  Evaluation 2

3 3

4  Two major types of packet classification algorithm ◦ Searching space partition  partition the searching space into smaller subspaces  Ex. RFC, HSM 4

5 ◦ Ruleset partition  cut the large ruleset into smaller ones  Ex. HiCuts, HyperCuts 5

6  Utilize dynamic heuristics to split the ruleset efficiently  Combine different data structures to optimize both time and space performance 6

7  Terminology ◦ E-Bits  some bits will partition the ruleset more “effectively”.  To partition ruleset into smaller sub-rulesets. ◦ M-Vector  Definition 3.1 (M-Vector): A M-Vector V is a bit vector that satisfies: V[i] = 1 only if bit i is an E-Bit, otherwise V[i] = 0. 7 0101

8 8 D-Table S-Block

9  Preparation Phase ◦ 1. E-Bits selection ◦ 2. M-Vector generation ◦ 3. D-Table construction 9

10  1. E-Bits selection ◦ Two problems  E-Bits choosing  Length optimization ◦ Solutions  Judging Function(J-Function)  Performance Function(P-Function) 10

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12 12

13  2. M-Vector generation ◦ Built with the process of E-Bits choosing and length optimization  Fast-Growth  Intelli-Swap(I-Swap) 13

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16  Classification Phase V H T 16

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19  IA based Implementation 19

20 ◦ Memory storage usage 20

21 ◦ Scalability  The ratio of Memory Per Rule (MPR) 21

22  Multi-core NP Implementation ◦ Cavium OCTEON CN5860, ACL10K 22

23  FPGA based Implementation ◦ Xilinx Virte-5 FPGA(XC5VSX240T), 2048 Kb of Block RAM 23

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