1. DUSD(Labs) GSRC Calibrating Achievable Design 11/02

2. 2 9/19/02 White Paper Notes #1: The DT Productivity Gap u GSRC focuses on critical problems in how chips are designed u Two approaches s Change the problem s Solve the problem more effectively t Roadmapping  What is the problem? t Reusable CAD-IP, standard evaluation frameworks  Solve it faster t Metrics  Measure to improve u A particular problem is the productivity of human designers s We work on CAD after all, not the design of new types of circuits s Compared to other ITRS technology requirements, designer productivity is a gray area t But it is as important a problem as power minimization t And it is ill-defined as a problem because human designer productivity losses are not well-documented

3. 3 9/19/02 Main Challenges u Calibration s What is “highest attainable” (for a given technology)? s Timeline / Roadmap of problem arrivals, methodology opportunities t Heterogeneous (SIP) integration, Logic SEU, Dynamic power, Parametric yield loss, … t With respect to Design Drivers u Specific solution strategies (methodologies) s E.g., inductance design (cf. Intel buffer overuse to suppress inductance effects) u Design process platforms s Reusable, composable solvers s Methodology and technology for design process optimization s Component-based, flexible, optimizable flows and methodologies s Common vehicles for research, transfer to industry, and education u Automation of the design of IC’s to the greatest extent possible

4. 4 9/19/02 Brilliant Ideas u Asymptotically scalable design and design technology productivity s Scalability == w.r.t. memory and runtime, designer effort, learning curves, … s METRICS  Design process health monitoring, design process optimization u Maximally flexible and reusable design process IP s Raise the level of abstraction for design process descriptions s Remove unnecessary levels of detail to facilitate reuse and composition s Simplify CAD tool evaluation and large-scale optimization of design flows/methodologies u Living Roadmap s Connect 9 disparate industry roadmaps via models of Drivers, as well as ITRS Overall Roadmap Technology Characteristics and individual Technology Areas s “Shared red bricks”: how Design Technology helps other technologies set, and then solve, Moore’s Law requirements

5. 5 9/19/02 Expected Outcomes u Prototype methodology implementations s based on open-source EDA software, industry suggestions, … u Automation on demand s Bookshelf.exe, methodologies for automated methodology optimization u Fundamental limits (+ normalization to cost) s E.g., interconnect t Back-end metrics (analogous to bandwidth) for stacks; slew and RLC metrics t Power, reliability, repeater/post-repeater envelopes s E.g., reliability t System-level reliability models, metrics, requirements, roadmap u Leading change (research interoperability, technology delivery, education), Living roadmap, Drivers roadmap, …

6. 6 9/19/02 Driver-Specific Roadmapping and Methodology Research — Large-scale DSP and DRAM Integration in Boeing STAP Processor u >100 GOPs/Watt DSP core being developed in DARPA MSP program. u 26 parallel high-speed DRAM access, 26 discrete DRAM chips, > 1000 IOs. u DRAM can not be embedded due to the cost and DRAM size required (> 150Mb). u Performance limited by DRAM interface; DDR or QDR DRAM increases design complexity and difficulty of skew management u Current solution duplicates DSP core, each copy accessing 13 DRAM chips (degrades performance 4X (2X area, 2X power) u SiP solution integrates conventional DRAM and DSP core in a package. Area-IO architecture enables the DRAM to be customized to provide high bandwidth access. Package routability analysis Thermal analysis and modeling Internal IO performance analysis GTX Framework SiP power/ground structure Memory architecture optimization STAP Processor SiP DRAM/Logic Integration DoD Applications Custom DRAM Design Driver Design Methodology Roadmap, Limits

7. 7 9/19/02 How This Fits Within GSRC u This is a cross-cut theme – it serves as both driver and environment (platform) for integrating work of many researchers within the center u Provides GSRC and other FRCs with quantified, self-consistent guidance on research focus, priorities, timelines u Reaches outside GSRC: “culture change” (open source, SIA-ITRS, metrics, …) u Supports other areas, brings publicity via more near-term transfer of research results