1. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 10: Data-Converter Example Spring 2009 W. Rhett Davis NC State University with significant material from Paul Franzon, Bill Allen, & Xun Liu

2. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 2 Announcements l HW#4 Due Thursday

3. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 3 Data Converter Specification l When a new 32-bit data word arrives at the input, the module stores it and then outputs the word as 4 bytes, starting with the MSB and ending with the LSB. l The arrival of a 32-bit word to be converted is signaled by a pulse on ready that is 3 clock cycles long. l The output of a byte of data is signaled by a one clock cycle pulse on new. The output byte is available during the new pulse and for one clock cycle after. Data Converter IN ready OUT new 32 / 8 /

4. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 4 Design Process l Step 1: Write Specification l Step 2: Draw Schematic » Ports » Registers » Datapath Logic » MUXes » Control Logic l Step 3: Write Verilog Code » Label Internal Signals » Map elements from schematic into code

5. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 5 Data Selector Schematic

6. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 6 Controller State Diagram

7. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 7 Data Converter (Simplified Style) module dataconv(IN, clock, ready, reset, OUT, new); input clock,reset,ready; input [31:0] IN; output [7:0] OUT; output new; Complete the module description

8. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 8 Data Converter (Simplified Style)

9. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 9 Data Converter (Simplified Style)

10. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 10 Data Converter (Sophisticated Style) module dataconv(IN, clock, ready, reset, OUT, new); input clock,reset,ready; input [31:0] IN; output [7:0] OUT; output new; reg [7:0] OUT; reg new; reg [31:0] value; reg [3:0] state; always @(posedge clock) begin if (reset) state <= 0; else case(state) 0: begin if (ready) state <= 1; else state <= 0; new <= 0; end 1: begin state <= 2; value <= IN; end 2: begin state <= 3; OUT <= value[31:24]; new <= 1; end

11. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 11 Data Converter (Sophisticated Style) 3: begin state <= 4; new <= 0; end 4: begin state <= 5; OUT <= value[23:16]; new <= 1; end 5: begin state <= 6; new <= 0; end 6: begin state <= 7; OUT <= value[15:8]; new <= 1; end 7: begin state <= 8; new <= 0; end 8: begin state <= 9; OUT <= value[7:0]; new <= 1; end 9: begin state <= 0; new <= 0; end default: begin state <= 0; end endcase end endmodule

12. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 12 Comparison of Styles l What will be the difference between the hardware synthesized from the simplified and sophisticated versions of the Data Converter code given in class?