1. ECE 448 Lab 3 FPGA Design Flow Based on Xilinx ISE and ISim. Using Seven-Segment Displays, Buttons, and Switches.

2. Part 1: Distribution and testing of FPGA boards Part 2: Seven Segment Displays Part 3: User Constraints File Part 4: Buttons and Switches Part 5: Introduction to FPGA Design Flow based on Xilinx ISE Part 6: Introduction to Lab 3 Part 7: Class Exercise Part 8: Demo Lab Assignment 2 Agenda for today

3. Part 1 Distribution and Testing of FPGA Boards

4. Part 2 Seven Segment Displays

6. 4-Digit Seven Segment Display

7. Patterns for Decimal Digits

8. Patterns for Hexadecimal Digits

9. Connection to FPGA Pins

10. Multiplexing Digits

11. Time-Multiplexed Seven Segment Display

12. Counter UP COUNTER UP Counter UP q(k-1..k-2) AN Counter UP SEG(6..0) Cou nter UP rst clk OC SSD_DRIVER OC – One’s Complement

13. Size of the counter 1 ms ≤ 2 k * T CLK ≤ 16 ms f CLK = 100 MHz k = ?

14. Part 3 User Constraint File (UCF)

15. File contains various constraints for Xilinx – Clock Period – Circuit Locations – Pin Locations Every pin in the top-level unit needs to have a pin in the UCF

16. Nexys 3

17. Nexys 3 User Constraint File (UCF) - SSD # Seven Segment Displays NET " SEG " LOC = "T17" | IOSTANDARD = "LVCMOS33"; NET " SEG " LOC = "T18" | IOSTANDARD = "LVCMOS33"; NET " SEG " LOC = "U17" | IOSTANDARD = "LVCMOS33 " ; NET " SEG " LOC = "U18" | IOSTANDARD = "LVCMOS33"; NET " SEG " LOC = "M14" | IOSTANDARD = "LVCMOS33"; NET " SEG " LOC = "N14" | IOSTANDARD = "LVCMOS33"; NET " SEG " LOC = "L14" | IOSTANDARD = "LVCMOS33 " ; NET " AN " LOC = "N16" | IOSTANDARD = "LVCMOS33"; NET " AN " LOC = "N15" | IOSTANDARD = "LVCMOS33 " ; NET " AN " LOC = "P18" | IOSTANDARD = "LVCMOS33 " ; NET " AN " LOC = "P17" | IOSTANDARD = "LVCMOS33 " ;

18. Nexys 3 User Constraint File (UCF) - LEDs # LEDs NET "LED " LOC = "U16" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "V16" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "U15" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "V15" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "M11" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "N11" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "R11" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "T11" | IOSTANDARD = "LVCMOS33";

19. # Clock NET "CLOCK" LOC = "V10" | IOSTANDARD = "LVCMOS33"; Nexys 3 User Constraint File (UCF) CLOCK

20. Nexys 4 DDR

21. Nexys 4 User Constraint File (UCF) – SSD ### 7 segment display NET "seg " LOC = "T10" | IOSTANDARD = "LVCMOS33"; NET "seg " LOC = "R10" | IOSTANDARD = "LVCMOS33"; NET "seg " LOC = "K16" | IOSTANDARD = "LVCMOS33"; NET "seg " LOC = "K13" | IOSTANDARD = "LVCMOS33"; NET "seg " LOC = "P15" | IOSTANDARD = "LVCMOS33"; NET "seg " LOC = "T11" | IOSTANDARD = "LVCMOS33"; NET "seg " LOC = "L18" | IOSTANDARD = "LVCMOS33"; NET "seg " LOC = "H15" | IOSTANDARD = "LVCMOS33"; NET "an " LOC = "J17" | IOSTANDARD = "LVCMOS33"; NET "an " LOC = "J18" | IOSTANDARD = "LVCMOS33"; NET "an " LOC = "T9" | IOSTANDARD = "LVCMOS33"; NET "an " LOC = "J14" | IOSTANDARD = "LVCMOS33"; NET "an " LOC = "P14" | IOSTANDARD = "LVCMOS33"; NET "an " LOC = "T14" | IOSTANDARD = "LVCMOS33"; NET "an " LOC = "K2" | IOSTANDARD = "LVCMOS33"; NET "an " LOC = "U13" | IOSTANDARD = "LVCMOS33";

22. Nexys 4 User Constraint File (UCF) - LEDs ## LEDs #NET "led " LOC = “H17"| IOSTANDARD = "LVCMOS33"; #NET "led " LOC = “K15"| IOSTANDARD = "LVCMOS33"; #NET "led " LOC = “J13"| IOSTANDARD = "LVCMOS33"; #NET "led " LOC = “N14"| IOSTANDARD = "LVCMOS33"; #NET "led " LOC = “R18"| IOSTANDARD = "LVCMOS33"; #NET "led " LOC = “V17"| IOSTANDARD = "LVCMOS33"; #NET "led " LOC = “U17"| IOSTANDARD = "LVCMOS33"; #NET "led " LOC = "U16"| IOSTANDARD = "LVCMOS33"; #NET "led " LOC = "V16"| IOSTANDARD = "LVCMOS33"; #NET "led " LOC = “T15"| IOSTANDARD = "LVCMOS33"; #NET "led " LOC = “U14"| IOSTANDARD = "LVCMOS33"; #NET "led " LOC = “T16"| IOSTANDARD = "LVCMOS33"; #NET "led " LOC = “V15"| IOSTANDARD = "LVCMOS33"; #NET "led " LOC = “V14"| IOSTANDARD = "LVCMOS33"; #NET "led " LOC = “V12"| IOSTANDARD = "LVCMOS33"; #NET "led " LOC = “V11"| IOSTANDARD = "LVCMOS33";

23. # Clock #NET "clk" LOC = "E3"| IOSTANDARD = "LVCMOS33"; Nexys 4 User Constraint File (UCF) CLOCK

24. Part 4 Switches and Buttons

26. Nexys 3

27. Nexys 3-User Constraint File (UCF) Switches # Switches NET " SW " LOC = "T10 " | IOSTANDARD = "LVCMOS33 " ; NET " SW " LOC = "T9" | IOSTANDARD = "LVCMOS33"; NET " SW " LOC = "V9" | IOSTANDARD = "LVCMOS33 " ; NET " SW " LOC = "M8 " | IOSTANDARD = "LVCMOS33 " ; NET " SW " LOC = "N8" | IOSTANDARD = "LVCMOS33 " ; NET " SW " LOC = "U8" | IOSTANDARD = "LVCMOS33 " ; NET " SW " LOC = "V8" | IOSTANDARD = "LVCMOS33 " ; NET " SW " LOC = "T5" | IOSTANDARD = "LVCMOS33 " ;

28. Nexys 4- User Constraint File (UCF) Switches ## Switches #NET "sw " LOC = “J15"| IOSTANDARD = "LVCMOS33"; #NET "sw " LOC = “L16"| IOSTANDARD = "LVCMOS33"; #NET "sw " LOC = “M13"| IOSTANDARD = "LVCMOS33"; #NET "sw " LOC = “R15"| IOSTANDARD = "LVCMOS33"; #NET "sw " LOC = "R17"| IOSTANDARD = "LVCMOS33"; #NET "sw " LOC = “T18"| IOSTANDARD = "LVCMOS33"; #NET "sw " LOC = “U18"| IOSTANDARD = "LVCMOS33"; #NET "sw " LOC = “R13"| IOSTANDARD = "LVCMOS33";

29. Nexys 4-User Constraint File (UCF) Switches(2) #NET "sw " LOC = “T8"| IOSTANDARD = "LVCMOS33"; #NET "sw " LOC = “U8"| IOSTANDARD = "LVCMOS33"; #NET "sw " LOC = “R16"| IOSTANDARD = "LVCMOS33"; #NET "sw " LOC = "T13"| IOSTANDARD = "LVCMOS33"; #NET "sw " LOC = “H6"| IOSTANDARD = "LVCMOS33"; #NET "sw " LOC = “U12"| IOSTANDARD = "LVCMOS33"; #NET "sw " LOC = “U11"| IOSTANDARD = "LVCMOS33"; #NET "sw " LOC = “V10"| IOSTANDARD = "LVCMOS33";

30. Buttons

31. Connection of Buttons to FPGA Pins

32. Debouncing Buttons Bouncing period typically smaller than 10 ms key bounce, t BOUNCE

33. Using DEBOUNCE_RED to Generate Short Pulses (1) RED – Rising Edge Detector

34. Using DEBOUNCE_RED to Generate Short Pulses (2)

35. Debouncer reset input clk output

36. Debouncer

37. k and DD Generics k - width of the counter used to measure the debouncing period DD - debouncing period in clock cycles Values of generics given on the next slide assume that the clock frequency = 100 MHz and thus clock period = 10 ns.

38. k and DD Generics Option 1 (value used for simulation only): DD = 100 assuming bouncing period < 1 μs = 1000 ns condition: DD*10ns = 1000 ns => DD = 100 k=7 because 2^7 > 100 Option 2 (values used for synthesis, implementation, and experimental testing): DD = 1000000 assuming bouncing period = 10 ms condition: DD*10ns = 10ms => DD = 1,000,000 k=21 because 2^21 > 1,000,000

39. Rising Edge Detector - RED Turn a step function into an impulse Allows a step to run a circuit for only one clock cycle Rising Edge Detector

40. clk input output input clk output rising edge detector reset

41. Connection of Buttons to FPGA Pins

42. # Buttons NET "BTNS" LOC = "B8" | IOSTANDARD = "LVCMOS33"; BTNS NET "BTNU" LOC = "A8" | IOSTANDARD = "LVCMOS33"; BTNU NET "BTNL" LOC = "C4" | IOSTANDARD = "LVCMOS33"; BTNL NET "BTND" LOC = "C9" | IOSTANDARD = "LVCMOS33"; BTND NET "BTNR" LOC = "D9" | IOSTANDARD = "LVCMOS33"; BTNR Nexys 3 User Constraint File (UCF) Buttons

43. ## Buttons #NET "btnCpuReset" LOC = "C12"| IOSTANDARD = "LVCMOS33"; #NET "btnC" LOC = “N17“ | IOSTANDARD = "LVCMOS33"; #NET "btnU" LOC = “M18"| IOSTANDARD = "LVCMOS33"; #NET "btnL" LOC = “P17" | IOSTANDARD = "LVCMOS33"; #NET "btnR" LOC = “M17"| IOSTANDARD = "LVCMOS33"; #NET "btnD" LOC = “P18" | IOSTANDARD = "LVCMOS33"; Nexys 4-User Constraint File (UCF) Buttons

44. Part 5 Hands-on Session on FPGA Design Flow based on Xilinx ISE and Xilinx ISim

45. Part 6 Introduction to Lab 3 Movie Ticket Dispensing Machine

46. Step 1: Choose a Movie BTNU (UP) BTND DOWN BTNR (RIGHT) BTNL LEFT BTNS (Enter) Default

47. BTNS (Enter) Step 2: Choose Ticket Quantity Use UP and Down buttons to change the quantity 18 + 13.5 + 9 + 9 = 49.50

48. Step 3: Entering Bills $1 UP $5 DOWN $20 RIGHT $10 LEFT Blink for 5 sec Total Amount Change

49. Step 4: Displaying Ad FREE POP CORN Fri 6-9

50. Part 7 Lab Exercise

51. 16-bit Binary Up-Down Counter

52. Counter UP COUNTER UP Counter UP q(k-1..k-2) AN Counter UP SEG(6..0) Cou nter UP rst clk OC SSD_DRIVER OC – One’s Complement

53. Lab Assignment 2: Demo Part 8