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Page 1EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Introduction to IC Test Tsung-Chu Huang ( 黃宗柱 ) Department of Electronic Eng. Chong Chou Institute of Tech.

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Presentation on theme: "Page 1EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Introduction to IC Test Tsung-Chu Huang ( 黃宗柱 ) Department of Electronic Eng. Chong Chou Institute of Tech."— Presentation transcript:

1 Page 1EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Introduction to IC Test Tsung-Chu Huang ( 黃宗柱 ) Department of Electronic Eng. Chong Chou Institute of Tech. Email: tch@dragon.ccut.edu.tw 2004/04/26

2 Page 2EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Bonus Project 1 1.Write a set of C (or C++) programs to read the ISCAS85 benchmark. 2.Construct an internal model (data structure). 3.Do functional logic simulation in the internal model. 4.Add a bit for fault insertion in each gate and do serial fault simulation.

3 Page 3EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Example for Proj#1/ (1) ISCAS85 Benchmark TDL Example MODULE : C17; INPUTS : I1gat, I2gat, I3gat, I6gat, I7gat; OUTPUTS : I22gat, I23gat; DESCRIPTION : TDL file created by Carafe of Hemlock USE : DEFINE : aoi21s_0(q=I7) = aoi21s(a1=I10,a2=I7gat,b=I13); ai2s_3(q=I10) = ai2s(a=I3gat,b=I6gat); ai2s_2(q=I22gat) = ai2s(a=I8,b=I12); i1s_1(q=I23gat) = i1s(a=I7); i1s_0(q=I13) = i1s(a=I12); ai2s_1(q=I12) = ai2s(a=I2gat,b=I10); ai2s_0(q=I8) = ai2s(a=I1gat,b=I3gat); END : MODULE;

4 Page 4EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Example for Proj#1/ (2) ISCAS85 Benchmark Verilog Example module C17(I1gat, I2gat, I3gat, I6gat, I7gat); input I1gat, I2gat, I3gat, I6gat, I7gat; output I22gat, I23gat; wire I7, I8, I10, I12, I13; // ISCAS85 C17 Circuits in Verilog aoi21s aoi21s_0(.q(I7),.a1(I10),.a2(I7gat),.b(I13)); ai2s ai2s_3 (.q(I10),.a(I3gat),.b(I6gat)); ai2s ai2s_2 (.q(I22gat),.a(I8),.b(I12)); ils ils_1 (.q(I23gat),.a(I7)); ils i1s_0 (.q(I13),.a(I12)); ai2s ai2s_1 (.q(I12),.a(I2gat),.b(I10)); ai2s ai2s_0 (.q(I8),.a(I1gat),.b(I3gat)); endmodule;

5 Page 5EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Example for Proj#1/ (3) TDL Parser and Internal Model #include #defineCALLOC(n,x)((x *)calloc(n,sizeof(x))) typedef struct line_struct LineType; struct line_struct { char *line, id[10], ip[6][10]; int im; /* max input lead */ char valid; int level; LineType *next; }; LineType *Head, *Tail; /* Head and Tail of */ typedef struct IDNode IDnode; struct IDNode { char *id; IDnode *next; }; IDnode *I[10000];

6 Page 6EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Example for Proj#1/ (4) TDL Parser and Internal Model main(argc, argv) int argc; char *argv[]; { FILE *tdlf; char firstname_tdl[20], str[100],s[30],*tok,*temp, ok, Y, F; LineType *t,*p,*q; int i; if(argc != 2) {printf("Usage: tdlr file \n"); exit(0);} strcpy(firstname_tdl,argv[1]); strcat(firstname_tdl,".tdl"); if((tdlf=fopen(firstname_tdl,"r"))==NULL) { printf("Open file error!\n"); exit(1);} do{ fgets(str,100,tdlf); printf("%s",str); sscanf(str,"%s ",s); }while( strcmp(s,"MODULE") ); do{ fgets(str,100,tdlf); printf("%s",str); tok=strtok(str,",;: "); }while(strcmp(tok,"INPUTS"));

7 Page 7EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Example for Proj#1/ (5) TDL Parser and Internal Model fgets(str,100,tdlf); printf("%s",str); tok=strtok(str,",;: "); Head=Tail=NULL; while(strcmp(tok,"OUTPUTS")){ t=CALLOC(1,LineType); t->im=0; t->valid=1; t->level=0; t->next=NULL; strcpy(t->id,tok); if(Head==NULL) Head=Tail=t; else {Tail->next=t; Tail=t;} fgets(str,100,tdlf); printf("%s",str); tok=strtok(str,",;: "); }

8 Page 8EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Example for Proj#1/ (6) TDL Parser and Internal Model fgets(str,100,tdlf); printf("%s",str); tok=strtok(str,",;: "); while(strcmp(tok,"DESCRIPTION")){ fgets(str,100,tdlf); printf("%s",str); tok=strtok(str,",;: "); } do{fgets(str,100,tdlf); printf("%s",str); tok=strtok(str,",;: "); }while(strcmp(tok,"DEFINE")); fgets(str,100,tdlf); temp=((char *)calloc(1,strlen(str)+1)); strcpy(temp,str); tok=strtok(str,"(=: ");

9 Page 9EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Example for Proj#1/ (7) TDL Parser and Internal Model while(strcmp(tok,"END")){ t=CALLOC(1,LineType); t->next=NULL; t->im=t->valid=t->level=0; t->line=temp; tok=strtok(NULL,"=)"); strcpy(t->id,tok); tok=strtok(NULL,"("); tok=strtok(NULL,",); "); while(tok!=NULL) { if(tok[0]==')'||tok[0]==';'||tok[0]=='\n') break; strcpy(t->ip[t->im++],tok); tok=strtok(NULL,",); "); } Tail->next=t; Tail=Tail->next; fgets(str,100,tdlf); temp=((char *)calloc(1,strlen(str)+1)); strcpy(temp,str); tok=strtok(str,"(=: "); }

10 Page 10EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Bonus Project 2 1.Be familiar with a test tool in this laboratory environment, say, SynTest, Mentor or Synopsys, e.t.c. 2.Try at least 3 instances in ISCAS89 benchmark, do the full- scan test syntheses and obtain the test patterns and report the associated parameters (i.e., fault coverage, test efficiency and approximated area overhead.)

11 Page 11EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Syllabus & Chapter Precedence Introduction Modeling Logic SimulationFault Modeling Fault Simulation Testing for Single Stuck Faults Test Compression Built-In Self-Test Design for Testability (II)

12 Page 12EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Testing for Single Stuck Faults 1.Test Generation: Random vs. Diterministic 2.ATPG for SSFs in Combinational Circuits 3.ATPG for SSFs in Sequential Circuits

13 Page 13EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Test Generation: Random vs. Deterministic Test Selection Fault Simulation Fault Dropping TE enough? Done No Fault Selection Test Generation Fault Simulation Fault Dropping TE enough? Done No

14 Page 14EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Test Generation: Random vs. Deterministic #patterns Test Efficiency 0 Test set generation time Expected time per pattern 0

15 Page 15EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT 5-Value Operations v/v f 0/0 00 1/1 10 1/0 D↓ 0/1 D↑ Notations AND 0 1 D D X 0 0 0 0 0 0 0 1 D D X 1DDX 00000 D D XXX 0 DX X XD 0 OR 0 1 D D X 0 D X 1 1 D 1 1DDX D XXX DX X1 11111 01DDX 11

16 Page 16EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Test Generation for Fanout-Free Tree 1. Set all values to X X X X X X X X X X X X X 2. Justify(l, ~v) X X 3. Propagate(l, v/v f ) Justify for Enabling

17 Page 17EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT State 2 Decision Process in Justification State 1 1 111

18 Page 18EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Decision Process in Justification 0 000001010011100101110 State 1 Branches of Decision Tree

19 Page 19EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Sub- Process Backtracking in Decision Tree A BCBC Conflict or Contradiction In typical circuits, test generation for some faults usually have more than thousands of backtracking

20 Page 20EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Test Generation for Fanout-Free Tree 1. Set all values to X X X X X X X X X X X X X 2. Justify(l, ~v) X X 3. Propagate(l, v/v f ) Justify for Enabling Possible Backtracking with Fanout If Conflict? Backtracking

21 Page 21EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Concept of Frontiers J-FrontierD-Frontier D-frontier: all gates with any D or \D on their inputs – a queue waiting for propagation. J-frontier: all gates keeping track of unsolved

22 Page 22EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Basic Test Generation Algorithm TG() { if( imply_and_check( ) ) { if ( error_at_PO and all_lines_justified ) return(1); if ( no error can be propagated to a PO) return(0); select an unsolved problem; for (all ways) { select a untried way to solve it; if (TG( ) ) return (1); } } else return(0); }

23 Page 23EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Implication Process Purposes 1.Compute all values that can be uniquely determined by implication. 2.Check for consistency and assign values. 3.Maintain the D-frontier and the J-frontier. Operations 1.Imply_and_check() retrieves in tern every entry in the assignment queue (like the time wheel in logic simulation).

24 Page 24EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Backward Implication 1 x x 1 1 0 x 1 0 1 0 x x g J-frontier ← J-frontier U {g} 1 xx x 11 1

25 Page 25EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Forward Implication: Binary Values x 0x0 1 1x1 x 00 J-frontier ← J-frontier \ {g} g x 10 g 0 E 1xE g D-frontier ← D-frontier \ {g} E 0x0 g

26 Page 26EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Forward Implication: Error Values x Ex g D-frontier ← D-frontier U {g} 1 ExE g E ExE g D-frontier ← D-frontier \ {g} Ex0 g E x Ex g D-frontier ← { } 1 E Unique Drive

27 Page 27EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT D-Algorithm Roth 1966 D_Algo() { if imply_and_check() if(error not at PO){ repeat{ select(g, D_frontier); enabling(g); if(D_algo()) return(SUCCESS); } until(all gates tried) return(FAILURE); } if(J_frontier) repeat{ select(g, J_frontier); select(input, g); select(input j, g); controlling(j, g); if(D_algo()) return(SUCCESS); enabling(j, g); } until(all gates tried); else return(SUCCESS); return(FAILURE); } Characteristic feature: Multiple-path sensitization, ability to propagate errors on several reconvergent paths.

28 Page 28EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Variety of PG Algorithms #values 5V 9V #Paths Single (PODEM) Multiple (D-algo) Sensitization or Desensitization ? Speeding Skills Dynamic/static learning

29 Page 29EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Example for D-Algorithm Schneider’s Circuit, 1967 d d’ h i e e’ j k f f’ l m b c a n g 0 1 1 D-frontier:________________J-frontier:________________ g 1 1 0 ikmn 1 1 1 1 0 1

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